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Restricts annotations to be string-based (and thus less typesafe)
Makes annotations more easily serializable and interact with Chisel
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* handle uninferred ports gracefully in RemoveCHIRRTL
memory port directions are not inferred during CInferMDir if not being used, so handle them properly in RemoveCHIRRTL
* fix CInferTypes
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Replace with more sensible comment to see LICENSE rather than including the
whole license in every file
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* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers
* Transforms define inputForm and outputForm
* Custom transforms can be inserted at runtime into compiler or the Driver
* Current "built-in" custom transforms handled via above mechanism
* Verilog-specific passes moved to the Verilog emitter
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While unsafe, this supports Verilog parameter types.
Tests now require Verilator 3.884+ to pass.
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Adds support for Integer, Double/Real, and String parameters in external
modules. Also add name field to extmodules so that emitted name can be
different from Firrtl name. This is important because parameterized extmodules
will frequently have differing IO even though they need to be emitted as
instantiating the same Verilog module.
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Transforms are new unit of modularity within the compiler.
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Including using different clocks and ports defined in when scope.
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compares to expected Verilog. Uses ScalaTest. Should be eventually replaced with actual simulation of rocket-chip
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