| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2017-01-29 | Keep firrtl's simulation environment in sync with chisel's. (#425) | Jim Lawson | |
| 2016-12-08 | Clk2clock - rename the implicit "clk" module input "clock" (#387) | Jim Lawson | |
| * Rename implict module "clk" input to "clock". This doesn't rename all the "self-contained" test instances. nor the memory "clk" enables, nor the implict module "clk"s in the regress .fir files. * Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances. This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files. | |||
| 2016-11-04 | Cleanup license at top of every file (#364) | Jack Koenig | |
| Replace with more sensible comment to see LICENSE rather than including the whole license in every file | |||
| 2016-05-03 | Make simulations that time out fail when run in firrtlTests | jackkoenig | |
| 2016-04-20 | Fix top.cpp reset race condition #137 | jackkoenig | |
| 2016-03-15 | Revamp string literal handling | jackkoenig | |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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