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2020-01-07Redirect testing shell commands to loggerJack Koenig
This includes the built-in functions in BackendCompilationUtilities which are a public API
2020-01-07Fix literals cast to Clocks in Print and StopJack Koenig
Many tools don't except 'always @(posedge 1'h0)' so we assign the literal to a wire and use that as the posedge target.
2020-01-07Remove unnecessary $signed casts for PrimOps in Verilog EmitterJack Koenig
[skip formal checks] Adds new InlineCastsTransform to the VerilogEmitter which removes Statements that do nothing but cast by inlining the cast Expression
2020-01-07Remove unnecessary casts in Constant PropagationJack Koenig
2020-01-06Verilog emitter transform InlineNots (#1270)John Ingalls
[skip formal checks] * ConstProp FoldEqual/FoldNotEqual propagate boolean (non-)equality with true/false * transform InlineNots * transform back-to-back Nots into straight rename * swap mux with inverted select Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
2020-01-06Remove incorrect --firrtl-source option (#1266)Schuyler Eldridge
This removes the incorrect short --firrtl-source option. This was supposed to be the helpValueName. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-01-06Make EmittedAnnotation Unserializable (#1288)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2019-12-30Minor code cleansup in InferResetsJack Koenig
* Move Map lookup into closure so it only occurs if necessary * Replace gender with flow and improve code clarity
2019-12-30Respect last connect semantics in InferResetsJack Koenig
InferResets will now support last connect semantics (within the same scope) when determining the concrete reset type for components of type Reset. This only includes *unconditional* last connects; it remains illegal to drive a component of type Reset with different concrete types under differing when conditions. For example, the following is now legal: input a : UInt<1> input b : AsyncReset output z : Reset z <= a z <= b The second connect will when and z will be of type AsyncReset. The following remains illegal: input a : UInt<1> input b : AsyncReset input c : UInt<1> output z : Reset z <= a when c : z <= b This commit also ensures that components of type Reset with no drivers (or only invalidation) default to type UInt<1>. This fixes a bug where the transform would crash with such input.
2019-12-18Improve Scaladoc (#1284)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-12-18Fix incorrect ScalaDoc link (#1282)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-12-16{Firrtl, Circuit}Option should be Unserializable (#1278)Schuyler Eldridge
FirrtlOption and CircuitOption represent, respectively, something that is convertible to FirrtlOptions or something that is convertible to a FirrtlCircuitAnnotation. Neither of these is intended to be serialized automatically in output JSON. This has the effect of *not* JSON-serializing the FirrtlCircuitAnnotation. This serialization is supposed to be to a file via an emitter. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-12-11Make the member 'logger' added by the trait LazyLogging protected. (#1271)Jim Lawson
The switch to using our own Logger triggered a latent bug, described in comments to #1258. Make the `val logger` introduced by the 'trait LazyLogging` protected.
2019-12-06Move --no-dedup from stage-global to firrtl-local (#1265)Schuyler Eldridge
This moves the --no-dedup option to be FIRRTL-stage specific as opposed to a global option common to all stages. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-12-03Logger tweaks (#1190)edwardcwang
2019-11-29Remove scala-logging fully in favor of our own loggerJack Koenig
There was some vestigial logging that conflicts with the homebrewed logger used by most of the codebase
2019-11-19Error when blackboxing memories with unsupported masking (#1238)Abraham Gonzalez
* Types containing bundles can't generally be converted to a single mask granularity * Update ReplSeqMemTests to check for illegal masks
2019-11-18Make updated type info available in VerilogMemDelays (#1243)Albert Magyar
* Closes #1242
2019-11-14Use getName instead of getSimpleNameSchuyler Eldridge
This changes uses of `getSimpleName` to `getName`. The former throws idiotic exceptions under Java 8, e.g., `getSimpleName` will fail if used on a class inside an object. This fixes a bug where any call to the `name` method of a custom transform defined inside an object (or in an environment wrapping things in objects like a REPL) will throw a malformed class name exception. E.g., if you do this and run with `-ll info` or your custom transform deletes annotations. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-11-07Add check for multiple sources for same wiring pin (#1191)Jack Koenig
2019-11-05Move CheckResets after CheckCombLoops (#1224)Jack Koenig
Recursive literal lookup needs to be guarded against combinational loops Added a test-case to illustrate the issue when CheckResets is run before CheckCombLoops
2019-11-04Merge branch 'master' into serialization-utilsJack Koenig
2019-11-04Ignore extmodule instances in Flatten (#1218)Albert Magyar
* Closes #1162 * Instances of extmodules remain in the final hierarchy * Extmodule definitions are not renamed or duplicated * The rest of the pass may proceed as normal
2019-11-04Add explicit EOF to top-level parser rule (#1217)Albert Magyar
* Fixes #1154 * Tests that #1154 example produces SyntaxErrorsException * Generally helps catch trailing syntax errors * Performance-neutral relative to previous grammar * Recommended by antlr4 devs, can help performance in some cases * See antlr/antlr4#1540
2019-10-31Guard initial blocks in emitted Verilog with `ifndef SYNTHESISJack Koenig
2019-10-29Remove an unneeded castDavid Biancolin
2019-10-29Some cleanupDavid Biancolin
2019-10-29Update src/main/scala/firrtl/annotations/JsonProtocol.scalaDavid Biancolin
Co-Authored-By: Jack Koenig <koenig@sifive.com>
2019-10-29Check that all annotations provide the typeHintDavid Biancolin
2019-10-29Try implementing recursive typeHint look upDavid Biancolin
2019-10-29Change findInstancesInHierarchy to return implicit top instanceAlbert Magyar
* Change FIRRTL-internal API, affecting only one corner case * Make API more "DWIM" and consistent with other methods * Add test cases for findInstancesInHierarchy * Update Scaladoc
2019-10-25Only emit the DeserilizationTypeHintsAnno when neededDavid Biancolin
2019-10-24Enhance CheckCombLoops errors with connection infoAlbert Magyar
* Closes #1203
2019-10-24Add EdgeData trait to mix in to graphsAlbert Magyar
* Add Scaladoc for EdgeData API * Include stringified vertices in EdgeNotFoundException
2019-10-24Supply a trait to allow user annotations to provide SERDES type hintsDavid Biancolin
2019-10-22Emit Verilog "else if" in register updatesSchuyler Eldridge
Modifies the Verilog emitter to emit "else if" blocks as opposed to more deeply nested "else begin if" blocks. This improves the output Verilog readability. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-21Fix write-first mem enable handling in VerilogMemDelaysAlbert Magyar
* Additional refactoring to clean up pass implementation * Make register names match old scheme to appease CI
2019-10-18Upstream intervals (#870)Adam Izraelevitz
Major features: - Added Interval type, as well as PrimOps asInterval, clip, wrap, and sqz. - Changed PrimOp names: bpset -> setp, bpshl -> incp, bpshr -> decp - Refactored width/bound inferencer into a separate constraint solver - Added transforms to infer, trim, and remove interval bounds - Tests for said features Plan to be released with 1.3
2019-10-08Make TopWiringTransform idempotentSchuyler Eldridge
This changes TopWiringTransform to remove TopWiringAnnotations after it runs. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-07Absorb some instance analysis into InstanceGraph, use safer boxed Strings ↵Albert Magyar
(#1186) * Replace instance analysis code with InstanceGraph API calls * Add convenience implicits for using TargetTokens as safe boxed strings
2019-10-03Add Block factory from argument list of Statements (#1197)Albert Magyar
2019-10-01Restore ResolveGenders to its status as a Pass (#1192)Jack Koenig
Fix minor regression from #1124
2019-09-30Implement read-first memories in VerilogMemDelaysAlbert Magyar
* Corrects behavior under write collisions * Avoids heavily refactoring pass
2019-09-30Add read-under-write checks for memory emissionAlbert Magyar
* Stop ignoring read-under-write (RUW) parameter * Add conservative check: blackbox only when RUW is "undefined" * VerilogMemDelays now throws InternalError for read-first memories * Previously, read-first mems were incorrectly implemented as write-first
2019-09-30Improve read-under-write parameter supportAlbert Magyar
* Make the read-under-write (RUW) parameter typesafe * Add RUW support to the FIRRTL proto and CHIRRTL grammar
2019-09-19Faster inline renaming (#1184)Albert Chen
* dont chain inline and refix RenameMaps * cache already inlined modules * reduce number of chained RenameMaps * InlineInstances: cleanup and add comments
2019-09-17Speed up InlineInstances (#1182)Jack Koenig
Create instance maps once for each Module
2019-09-16Deprecate Gender and add implicit Flow conversionSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-16Rename gender to flowSchuyler Eldridge
The following names are changed: - gender -> flow - Gender -> Flow - MALE -> SourceFlow - FEMALE -> SinkFlow - BIGENDER -> DuplexFlow - UNKNOWNGENDER -> UnknownFlow Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-12Add space, s/Github/GitHub/ in DontTouchException (#1177)Schuyler Eldridge
Adds a space to correct in an exception message. Corrects capitalization in Github to it's official name (GitHub) and adds a link to file an issue. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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