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2016-01-16Moved back to create-exps instead of fast-create-exps to fix bug - ↵azidar
fast-create-exps still needs debugging
2016-01-16Nodes must now be ground typesazidar
2016-01-16Fixed up minor errors after rebase onto masterazidar
2016-01-16Reworked Verilog emission of registers to if/else instead of ?:azidar
2016-01-16No longer split on muxesazidar
2016-01-16Commented back in Starting and Finishing for testingazidar
2016-01-16Sped up remove access by checking a conditionazidar
2016-01-16Added more data in printout of time to compileazidar
2016-01-16printf no longer includes a new lineazidar
2016-01-16Verilog emission no longer casts input to shr or bit selectazidar
2016-01-16Added hashed on get flipazidar
2016-01-16Sped up some passes. Added global mname to allow easy per-module hashes for ↵azidar
accellerating functions
2016-01-16Made create-exps a bit fasterazidar
2016-01-16Finished first cut at new firrtl - time for testing! Chirrtl requires masks ↵azidar
to be specified with write and rdwr mports
2016-01-16Fixed a bunch of tests, and minor bugsazidar
2016-01-16Added src and test filesazidar
2016-01-16WIP adding chirrtlazidar
2016-01-16WIP Almost there, need to generate enable connectionsazidar
2016-01-16WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit ↵azidar
roadblock in assigning clocked ports
2016-01-16WIP getting through testsazidar
2016-01-16Finished supporting nested accesses. Required some nuianced thinking. Pass ↵azidar
all feature tests. Deleted CondRead because it tested a problem we don't have any more
2016-01-16WIP, hit semantic bug in WSubAccessazidar
2016-01-16New memory works with verilog. Slowly changing tests and fixing bugs.azidar
Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
2016-01-16WIP. Compiles and almost done with verilog backend. Need to think about ↵azidar
emitting ports (and the assignments to them)
2016-01-16WIP. Compiles and there's some outputazidar
2016-01-16WIP. Compiles, need to testazidar
2016-01-16WIPazidar
2016-01-16WIP need to correctly output readwrite portsazidar
2016-01-16Merge branch 'scala' of github.com:ucb-bar/firrtlazidar
2016-01-16Added some commentsazidar
2016-01-16Printf no longer adds a new lineazidar
2016-01-16shift right does not cast input as signedazidar
2016-01-16Extraction inputs are no longer castazidar
2016-01-16Width of multiply is sum of input widthsazidar
2016-01-16Removed print statementsazidar
2016-01-16Fixed inline-indexers bug where genders weren't properly calculated inazidar
Lower Types pass. #53
2016-01-16Moved integer declaration inside module to be verilog (not system-verilog) ↵Adam Izraelevitz
compliant
2016-01-16Stop now emits correct verilog to stop simulation, required passing a string ↵azidar
not and integer
2016-01-16Fixed bug in printf and stop to correctly print to STDERRazidar
2016-01-16Finished adding clocks to Stop and Printazidar
2015-12-11Add a renameall pass that renames nodes according to a user-providedPaul Rigge
map. Also rewrite main so stanza and scala passes can be intermixed.
2015-12-11Added LoFirrtl compiler, can be called with -X lofirrtlazidar
2015-12-08Refactored MIDAS code into its own repojackkoenig
2015-12-07Fixed bug, I think transformation works now for the most partjackkoenig
2015-12-07The transformation works! Kind of, it works fine when everything is alwasy ↵jackkoenig
ready, has some weird issues when they're not, but also kind of works in that the hardware verifier still reports the right answer, it seems to go to half duty cycle and then do every token twice
2015-12-06Working on generating SimTop, need to figure out how to split the top-level ↵jackkoenig
IO between the sim modules.
2015-12-04Everything is broken, need Translator to work on files without a circuit, ↵jackkoenig
need to parse queue module text in midas/Utils.scala, need to create (src, dst) -> Module mapping in midas/Fame.scala
2015-12-03Some stylistic changes and a couple bugfixes to simulation wrapper generationjackkoenig
2015-12-03New wrapper generator completejackkoenig
2015-12-03Changing simwrapper to group ports that go to different places, not quite ↵jackkoenig
there yet. Will allow simple bulk connecting at top-level
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