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2016-06-10Fix Verilog codegen for regAndrew Waterman
Previously, we emitted if-else sequences for reg updates. Recent improvements to FIRRTL resulted in the emission of explicit mux networks instead. While equivalent, doing so reduces QoR, presumably because ECAD tools are tuned to the habits of manual Verilog coders. This seems to be a result of WRefs appearing between the regs and muxes. Chasing down the sources of the WRefs corrects the code generation. This patch reduces the Rocket pipeline area by about 2% and improves rocket-chip's Verilator performance by about 8%.
2016-06-09Initializes register addresses. (#189)Adam Izraelevitz
Fixes #187.
2016-06-09Merge branch 'master' into fix-warningAdam Izraelevitz
2016-06-08Fix for bug introduced in #174azidar
Addresses #184 Problem was that the width inferencer must assume a minimal width for self-referencing widths contained in a MaxWidth. Otherwise, it cannot solve the constraint.
2016-06-07Merge pull request #179 from sdtwigg/fixminwidthAdam Izraelevitz
Fix bug in FIRRTL width inference, refactor associated functions
2016-06-07Merge pull request #153 from ucb-bar/update-check-high-formAdam Izraelevitz
Update check high form
2016-06-07Merge pull request #182 from ucb-bar/bringup-hwachaAdam Izraelevitz
Guard mem read ports with random data if read addr is out of range
2016-06-07Fix non-thread safe Serialize by splitting it into class and objectJack Koenig
2016-06-06Fix bug in FIRRTL width inference, refactor associated functionsStephen Twigg
When folding over lists for MinWidth and MaxWidth, would assume 0 as a start value. 0 persists through MinWidth resulting in under-constraining The functions were also refactored to be more readable and aligned with scala style/best practices.
2016-06-06Guard mem read ports with random data if read addr is out of rangejackkoenig
Add function for diff assignments for sim and synthesis to VerilogEmitter Fixes #155
2016-06-01Suppress "match may not be exhaustive" warningAndrew Waterman
2016-05-24Remove prefix checking from Check High Formjackkoenig
Made obsolete by #120
2016-05-24Added Errors class and fixed tests.azidar
Canonicalizes catching/throwing PassExceptions.
2016-05-24add better type mismatch error messageColin Schmidt
also check for it int unittest
2016-05-24Remove nested AND in creation of readwrite ports for mems.jackkoenig
Fixes #147
2016-05-24Fix LowerTypes to check for wmode instead of rmodejackkoenig
2016-05-12Restructured Compiler to use Transforms. Added an InlineInstance pass.Adam Izraelevitz
Transforms are new unit of modularity within the compiler.
2016-05-12Implement File Infojackkoenig
2016-05-11Remove trait StanzaPass and related dead codejackkoenig
2016-05-10Remove old SplitExp pass (replaced by SplitExpressions)jackkoenig
2016-05-10Modified Verilog compiler to use new passesAdam Izraelevitz
RemoveValidIf, SplitExpressions, and PadWidths
2016-05-10Added RemoveValidIf pass.Adam Izraelevitz
This is to start moving stuff out of Emitter and into separate passes
2016-05-10Added new (and correct) Split Expressions passAdam Izraelevitz
2016-05-10Added pad widths to eliminate all implicit width extendingAdam Izraelevitz
2016-05-10Added constant propagation rule for greater/less thansAdam Izraelevitz
2016-05-10Fixed emission of memory ports to all be in the same always @ clock.Adam Izraelevitz
Changed initialization to assign the correct number of random bits.
2016-05-03Remove line in Verilog Emitter erroneously printing ); before module defjackkoenig
Fixes #133
2016-05-03Refactor Check Initialization to trace voids through temporary nodesjackkoenig
2016-05-03Make style and spacing of Check Initialization more idiomatic Scalajackkoenig
2016-05-03Move Check Initialization to its own filejackkoenig
2016-05-03Rewrite ExpandWhens to memoize complex default valuesjackkoenig
Fixes #113 and Fixes #150
2016-05-03Change style and spacing of Expand Whens to be more idiomatic Scalajackkoenig
2016-05-03Move ExpandWhens to its own filejackkoenig
2016-05-03Add Utils function getDeclarationjackkoenig
2016-05-03Move splitRef and mergeRef from LowerTypes to Utilsjackkoenig
Make EmptyExpression part of WIR
2016-05-03Add HasInfo trait to IR, IsDeclaration mixes in HasInfojackkoenig
Change Field from IsDeclaration to HasName Make WDefInstance an IsDeclaration
2016-04-29Change PassUtils to use Utils.time functionjackkoenig
2016-04-29Cleanup Parser comments and imports - No functional changesjackkoenig
2016-04-29Add timing to Parserjackkoenig
2016-04-29Add time function to Utilsjackkoenig
time uses LazyLogging, also delete import PrimOps._ (cyclic reference)
2016-04-26Make sure nested expressions don't make it to the EmitterAndrew Waterman
2016-04-26Split ValidIf from within PrimOpsAndrew Waterman
2016-04-26Fixed the check for bundle equality to allow relative flips to be wrong, but ↵Adam Izraelevitz
the leaf directions are the same
2016-04-26Added flag to parser to turn off using source locators. This allows for ↵Adam Izraelevitz
easier testing, because we don't the source locator information to say a test fails
2016-04-26Fixed bug in recursive check for whether BundleType contains flips.Adam Izraelevitz
2016-04-22Add Uniquify Passjackkoenig
Also add pass to Verilog Compiler list of passes This pass appends '_' to the names of aggregate types that would cause a name collision during LowerTypes.
2016-04-22Refactor LowerTypesjackkoenig
Make loweredName a public utility function of the Pass
2016-04-22Move LowerTypes to its own filejackkoenig
2016-04-22Add utility functions for coverting and computing Gender and Flipjackkoenig
2016-04-22Add isGround and isAggregate functions to Type Utils.jackkoenig
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