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* Conf file info is passed in through annotations.
* A pass should have its own set of sub-arguments delimited by :
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* Instead of filling the whole data width
* Added helper functions in MemUtils
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* Note, this version uses Albert's toBitMask function,
* which expands the bit mask to be the full data width (similar to Chisel2 output)
* Black boxes only have wmasks as needed
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* Annotate reference
* Changed memory port names to RWx, Wx, Rx, etc. and reconnected nodes
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* Was originally adding one extra set of things (to -> until)
* MemPortUtil conditionally includes wmask, if necessary
Changed endian-ness of write data/mask to match convention (little endian)
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* Annotates all sequential memories that can be black boxed.
* Annotates sequential memories that don't need write masks.
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* Corrected names to match current RW port spec
* Added Jack's Namespace on Circuit
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this eliminates warnings in recent versions of VCS
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Before, the verilog emitter would connect registers to the invalid ports
and use random initialization on the generated registers.
It is better to generate wires instead and use random assignment on the
wires.
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We previously had `ifdef guards on some parts of the emitted verilog to
control whether some registers or nets should be given random initial
values. These guards were all dependent on the RANDOMIZE macro.
However, there were actually three separate cases being controlled
1. Giving random values to disconnected wires
2. Random initialization of registers
3. Random initialization of memories
It is possible that the designer would want to switch these three on or
off independently in simulation. For instance, the latter two are
usually safe because registers and memories will get some definite
binary value at power on in the actual circuit, but the first one can
be quite dangerous because the undriven wire could be metastable.
This change provides separate macros for each of the three sets of
guards so that they can be controlled independently.
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* Updated FIRRTL spec + related code for readwrite ports.
(write) data -> wdata & mask -> wmask for clarity
* Also removed simple.fir that snuck into master branch.
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Now prints usage when given incorrect arguments
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* Removed stanza implementation/tests.
In the future we can move the stanza tests over, but for now they should
be deleted.
* Added back integration .fir files
* Added Makefile to give Travis hooks
* Added firrtl script (was ignored before)
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read port enables for cmems should always be high
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Creating the output file preemptively screws up make, as on
subsequent executions of make, it thinks the task succeeded.
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Bugfix: recursing stmts to remove unknown widths
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* Added RemoveEmpty.scala, which removes Empty and nested Blocks
* Reused squashEmpty from ExpandWhens by moving it to Utils
* Squash EmptyStmts in ExpandWhens correctly
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Change serialize to abstract method on FirrtlNode
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Fix mem infer
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turned on with '--inferRW <circuit name>'
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Fix use of global state in instance loop checking
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Change default log level to warn
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Refactor RemoveAccesses and fix bug #210.
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Also increase sensitivity of thread safety checking
Fixes #159
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Added corresponding unit test.
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ConstProp before width padding causes errors for SIntLiteral
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Then calls InferTypes to propagate inferred widths to expressions.
Required upgrading InferTypes to do simple width propagation.
Fixes #206 and #200.
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read ports are declared outside when clauses and used multiple times, so their enables should be inserted when being replaced
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Conflicts:
src/main/scala/firrtl/Compiler.scala
src/main/scala/firrtl/LoweringCompilers.scala
src/main/scala/firrtl/passes/Inline.scala
src/test/scala/firrtlTests/AnnotationTests.scala
src/test/scala/firrtlTests/InlineInstancesTests.scala
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Added a Chirrtl check for undeclared wires, etc.
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Removed InferWidths after ExpandWhens
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