sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-09-27	remove unnecessary parentheses	chick

2016-09-27	enclosing block redundant	chick

2016-09-27	No return type for implicit function	chick

2016-09-27	Anonymous function convertible to a method value	chick

2016-09-26	Added max width check to dshl shift amount (#318)	Adam Izraelevitz
	Address #297
2016-09-25	Spec features added: AnalogType and Attach (#295)	Adam Izraelevitz
	* Spec features added: AnalogType and Attach AnalogType(width: Width): - Concrete syntax: wire x: AnalogType<10> - New groundtype, very restricted in use cases. - Can only declare ports and wires with Analog type - Analog types are never equivalent, thus if x and y have Analog types: x <= y is never legal. Attach(info: Info, source: Expression, exprs: Seq[Expression]): - Concrete syntax: attach x to (y, z) - New statement - Source can be any groundtyped expression (UInt, SInt, Analog, Clock) - Exprs must have an Analog type reference an instance port - Source and exprs must have identical widths Included WDefInstanceConnector to enable emission of Verilog inout Should be mostly feature complete. Need to update spec if PR gets accepted. * Fixed bug where invalidated ports aren't handled * Bugfix for VerilogPrep Intermediate wires for invalidated instance ports were not invalidated * Bugfix: calling create_exp with name/tpe Returns unknown gender, which was passing through Caused temporary wire to not be declared Because Verilog is dumb, undeclared wires are assumed to be 1bit signals * Addressed donggyukim's style comments * Reworked pass to only allow analog types in attach Restrict source to be only wire or port kind Much simpler implementation, almost identical functionality Clearer semantics (i think?) * Fixup bugs from pulling in new changes from master * comments for type eqs and small style fixes
2016-09-25	offload latency pipe generation for memories from VerilogEmitter	Donggyu Kim
	discussed with @azidar
2016-09-25	more readable verilog generation for register updates	Donggyu Kim

2016-09-25	Syntactic sugar says use (A, B) instead of Tuple2[A, B]	chick

2016-09-25	use sys.error instead of deprecated error	chick

2016-09-25	stuff like this mutable.LinkedHashMap needs the mutable prefix	chick

2016-09-25	remove unnecessary blocks	chick
	example 1 s"${x}" example 2 case blah => { ??? }
2016-09-25	implicit functions should specify return type	chick

2016-09-25	use name parameter when calling a function with boolean constant	chick

2016-09-25	Change file name ReplacesSubAccesses ReplaceAccess	chick

2016-09-25	convert all occurencess of BigInt == Int to BigInt == BigInt	chick

2016-09-25	Fix Anonymous function convertible to a method value	chick
	if methods has parens, then referencing without parens is a method value, you don't need following underscore
2016-09-25	Minor fixes, typo in word	chick
	missing declarations in scala doc
2016-09-25	Use empty-parens as appropriate for f: => Unit calls	chick

2016-09-23	use .count instead of filter and size	chick

2016-09-23	Use parens on Unit methods	chick

2016-09-23	use .isEmpty, .nonEmpty, isDefined	chick

2016-09-23	use .indices	chick

2016-09-23	use .head instead of (0)	chick

2016-09-22	Fixed width inference for add, sub (#312)	Adam Izraelevitz
	Fixes #308 Fixes #193
2016-09-21	Fix clock connections in InferReadWrite (#310)	Donggyu

2016-09-21	swap functions in MemPortUtils and MemTransformUtils properly for further ↵	Donggyu Kim
	refactoring
2016-09-21	refactor AnnotateValidMemConfigs	Donggyu Kim

2016-09-21	refactor ReplaceMemMacros	Donggyu Kim

2016-09-21	refactor UpdateDuplicateMemMacros	Donggyu Kim

2016-09-21	clean up ReplSeqMem	Donggyu Kim

2016-09-21	refactor AnnotateMemMacros	Donggyu Kim

2016-09-21	refactor InferReadWrite	Donggyu Kim

2016-09-21	generalize Analysis.getConnects for code resuse	Donggyu Kim

2016-09-16	fill empty module body with "begin end" (#305)	Yunsup Lee
	* fill empty module body with "begin end" apparently vivado treats an empty module as a black box and triggers an error * Changed empty module to use always @(*) begin end
2016-09-15	Fix non-determinism bug in ExpandWhens (#303)	Jack Koenig
	Despite the fact that LinkedHashMaps preserve insertion order in traversal, it appears that .keys and .keySet return Sets that do not provide the same guarantee
2016-09-14	fix spaces in WIR.scala	Donggyu Kim

2016-09-14	style fixes for Compiler.scala, LoweringCompiler.scala	Donggyu Kim

2016-09-14	Fix for more general case of getConnectOrigin with reg feedback (#301)	Angie Wang

2016-09-14	fix enable signal inferecne for smems' read ports (#289)	Donggyu

2016-09-14	Fixed infinite loop for finding connect origin in ReplSeqMem (#300)	Angie Wang
	* Addressed the fact that a node can be connected to itself (updating reg)
2016-09-13	Fix a lurking width-inference bug; improve adjacent style (#298)	Andrew Waterman
	ceil(log(x) / log(2)) does not, in general, round to ceil(log2(x)). I noticed this because of #297.
2016-09-13	use BoolType for UIntType(IntWidth(1))	Donggyu Kim

2016-09-13	remove VIndent	Donggyu Kim

2016-09-13	use case object for WVoid, WInvalid	Donggyu Kim

2016-09-13	cache IntWidths to avoid redudant object creations	Donggyu Kim

2016-09-13	use case object for Kind	Donggyu Kim

2016-09-13	clean up PadWidth	Donggyu Kim

2016-09-13	clean up LowerTypes	Donggyu Kim
	no vars for mname, info
2016-09-13	clean up Passes.scala	Donggyu Kim