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2020-05-26[API change] Absorb repetitive WIR nodes into IRAlbert Magyar
* Absorb WRef into Reference * Absorb WSubField into SubField * Absorb WSubIndex into SubIndex * Absorb WSubAccess into SubAccess * Absorb WDefInstance into DefInstance ------------------------- API CHANGE SEVERITY -------------------------- This is projected to not break source-level compatibility with any known user code. However, it will break *binary* compatibility with all existing user FIRRTL passes, as is generally allowed with major releases of FIRRTL. --------------------------- DESCRIPTION -------------------------------- Previously, there were several nodes in WIR.scala that had a one-to-one correspondance with existing nodes in the standard firrtl.ir hierarchy. These nodes would have a case class resembling the corresponding standard IR node, but with the addition of one or more "analysis" fields. Since these fields (such as kind) represent helpful info that can be invalidated or set to Unknown (e.g. UnknownKind for Kind), it does not cause any issues to simply include these fields on any in-memory representation of FIRRTL IR. Although other systems for tracking FIRRTL analyses have evolved over time, the ubiquity of pattern-matching on these fields has lead most core and custom transforms to be written against WIR, rather than IR. This PR unifies the IRs by adding the fields that would be in an "augmented" WIR node directly into the corresponding IR node; i.e., the "type" and "kind" fields from WRef are added directly to the definition of the Reference case class, while these "repetitive" WIR case classes are removed entirely. -------------------- SOURCE-COMPATIBILITY ADAPTERS --------------------- Several object methods are added to WIR.scala to maintain source-compatiblity for passes that used WIR. These objects define factory methods and unapply methods, so passes that relied on implicit case class factories or pattern matching for the removed WIR types will remain perfectly source-compatible. However, these do not guarantee compatibility at the binary level. The types of the removed WIR case classes are also added as type aliases to the top-level firrtl package, which allows code that relies on explicit constructor calls or reflection to retain source-compatibility. Finally, additional explicit factory methods are added to the companion objects of the newly-augmented IR case classes, which allows user code to avoid having to specify any of the new analysis fields. Existing code that created non-WIR IR nodes will be able to continue using the previous factory signatures, which will cause all omitted analysis fields to be set to Unknown. ---------------------- UNMITIGATED API CHANGES ------------------------- While passes that used WIR will be source-compatible with this change, there is one significant change that affects any pass currently using non-WIR IR: the signatures of pattern-matching cases for Reference, SubField, SubIndex, SubAccess, and DefInstance must change to accommodate the extra fields. This cannot be worked at the API level due to restrictions on unapply overloading, but it could theoretically be solved with macros or other static rewriting. However, only four core transforms (RemoveProto, ToWorkingIR, Dedup, and RemoveChirrtl) use non-WIR IR, and it is expected that no user code currently relies on it, so the expected migration strategy is simply to change the small fraction of code relying on these nodes.
2020-05-22Do not throw NonFatal exceptions in annotation loggingJack Koenig
If an annotation cannot be serialized by json4s, we should not throw exceptions when doing trace-level logging.
2020-05-22DRY out transform running and annotation remappingJack Koenig
2020-05-21RenameMap: remove implicit rename chaining (#1591)Albert Chen
* RenameMap: remove implicit rename chaining * RenameMap: remove trailing comma Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-20Add scaladoc for LogicNode and tighten LowForm-only constraint (#1635)Albert Magyar
2020-05-18Don't try deduping the main module of a circuit (#1594)Albert Magyar
2020-05-18Fix equivalence tests (#853)Albert Chen
* - modify firrtlEquivalenceTest to use yosys equiv_simple/equiv_induct instead of miter - add RemoveValidIf pass to MinimumLowFirrtlOptimization * add EquivalenceTest to FirrtlSpec.scala, make classes in IntegrationSpec.scala abstract * change types of inputForm/outputForm to CircuitForm * change EquivalenceTest message * remove ICache equivalence tests * fix rebase errors * Add Ops scalatests to LEC suite * Only run compiler-path-comparison LEC tests on Ops design * Fixup issues with merge Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-05-18Canonicalize init of regs with zero as reset in RemoveReset (#1627)Albert Magyar
* Fixes #1561 * Add test for zero-reset reg from #1561
2020-05-14Make find_port return Unit and use Foreachers in ResolveKindsAlbert Magyar
2020-05-14Eliminate unnecessary traversals in ResolveKindsJack Koenig
2020-05-14Use HashMap instead of LinkedHashMap in ResolveKindsJack Koenig
2020-05-14Move Reg/Mem initializations to end of module (#1613)Deborah Soung
* Move reg/mem initializations to end of module * Add comment before reg/mem init if inits exist
2020-05-13Remove accidental hashing of all Modules in DedupJack Koenig
2020-05-13Remove expensive .distinct in DedupJack Koenig
2020-05-13Remove a redundant Expression traversal in InferTypesJack Koenig
2020-05-13Use HashMap instead of LinkedHashMap in InferTypesJack Koenig
Do the same in CInferTypes
2020-05-13Add --change-name-case <lower|upper> optionSchuyler Eldridge
Adds an options to the FIRRTL compiler command line to schedule the LowerCaseNames and UpperCaseNames transforms. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-13Add features.{LowerCaseNames, UpperCaseNames} transformsSchuyler Eldridge
Creates the features package and populates it with two new transforms: LowerCaseNames and UpperCaseNames. These transforms convert all names in a FIRRTL circuit to lower case or upper case. This is intended to help align generated Verilog with the policies of the company/institution using it. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> squash! Add LowerCaseNames and UpperCaseNames transforms
2020-05-13Refactor RemoveKeywordCollisions->ManipulateNamesSchuyler Eldridge
Generalize the operations of the RemoveKeywordCollisions transform into a new ManipulateNames transform. The ManipulateNames transform is an abstract transform for making conditional modifications to keywords/names in a FIRRTL circuit. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-13consolidated wire+assign to just wire, with expression inlined (#1600)Murali Vijayaraghavan
* consolidated wire <type> x; assign x = y; to wire <type> x = y; * Remove dead code from Emitter.scala Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
2020-05-11Have AppendInfo use MultiInfo, rather than appending with : (#1580)Adam Izraelevitz
* Bugfix - have AppendInfo use MultiInfo, rather than appending with : * Address reviewer feedback Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-11Add andr, orr, xorr literal constant propagationSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-05-08Don't check Types of Expressions in CheckHighFormLikeJack Koenig
Expression Types are derived. They cannot cause the errors detected by CheckHighFormLike independently of the user-specified types that remain chedked. This speeds up CheckChirrtl and CheckHighForm substantially.
2020-05-08Lazily generate more detailed error messages in CheckHighFormLikeJack Koenig
Don't serialize Expressions unless there is an error
2020-05-08deprecating BackendCompilationUtilities trait for object (#1575)Deborah Soung
2020-05-05before/after initial block macros (#1550)Deborah Soung
* adding init macros * fix missing tick * adding more documentation; fixing up emitter tests * adding initial-guarding macro test * prefixing macros with FIRRTL * cleanup * typo fix Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-04Add LegalizeAndReductionsTransformJack Koenig
Workaround for https://github.com/verilator/verilator #2300 present in Verilator versions v4.026 - v4.032. This transform turns AND reductions for expressions > 64-bits into an equality check with all ones. It is included as a prerequisite for all Verilog emitters.
2020-05-01Add missing invalidations to some transforms (#1541)Schuyler Eldridge
This adds missing invalidations to four transforms: - ExpandConnects - RemoveAccesses - SplitExpressions - VerilogMemDelays This necessarily updates test cases which expect exact transform orders to reflect the new order. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-05-01Emitter: guard _RAND_* declarations with ifdef (#1548)Albert Chen
* Emitter: add declare functions ifdef guard * Emitter: add ifdef initials * Emitter: add comments, cleanup * Emitter: changes from code review - make new methods private - use .withDefault - remove empty initial block Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-27Fix remaining 'removed in 1.3' deprecations (#1542)Albert Magyar
* Bump old 'removed in 1.3' deprecation * Remove outdated passes.VerilogRename * Fixes #1467
2020-04-22s/dependents/optionalPrerequisiteOf/Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Add optionalPrerequisiteOf, deprecate dependentsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Avoid repeated set construction in WiringTransform invalidatesSchuyler Eldridge
Co-authored-by: Jack Koenig <koenig@sifive.com> Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Mixin DependencyAPIMigration to all TransformsSchuyler Eldridge
This mixes in the new DependencyAPIMigration trait into all Transforms and Passes. This enables in-tree transforms/passes to build without deprecation warnings associated with the deprecated CircuitForm. As a consequence of this, every Transform now has UnknownForm as both its inputForm and outputForm. This PR modifies legacy Compiler and testing infrastructure to schedule transforms NOT using mergeTransforms/getLoweringTransforms (which rely on inputForm and outputForm not being UnknownForm), but instead using the Dependency API. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Add ExpandPrepares wrapperSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Add IdentityLike mix-in for TransformLikeSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Add trait-based Dependency API migration pathSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Use private LinkedHashSets in DependencyManagerSchuyler Eldridge
Changes the DependencyManager to use the private[options] LinkedHashSet members that shadow the public Seq[_] dependencies. This should avoid some unnecessary set construction and also improves readability of the DependencyManager code. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-22Fix typo in private DependencyAPI memberSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-20Avoid using infix for mutable append in CheckWidthsAlbert Magyar
2020-04-20Ensure arguments to asClock / asAsyncReset are single-bitAlbert Magyar
2020-04-14Avoid infinite loops on async-reset self-inits in CheckResetsAlbert Magyar
* Fixes #1516 * Tighten up logic for "casted literal" checking
2020-04-14Allow casts in AsyncReset literal value check (#1523)Jack Koenig
Chisel emits all literals as UInts cast to the correct type, make CheckResets support casts when checking that async reset registers are reset to literal values. Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-13Ensure PadWidths is run in mverilog compilerAlbert Magyar
2020-04-13Check EmitAnnotation class before emittingSchuyler Eldridge
Fixes a bug where an Emitter was only checking for the presence of an EmitCircuitAnnotation or EmitAllModulesAnnotation to control its emission flavor (one-file-per-module or one-file). This changes the check to ensure that the class of emitter matches that of the annotation. This allows for correct behavior when mixing different emitters, e.g., -E high -e middle. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-04-13Split Checks into separate filesAlbert Magyar
2020-04-13Split Resolves into separate filesAlbert Magyar
* Remove unused imports
2020-04-13move asyncInitials inside initial block RANDOMIZE ifdef (#1510)John Ingalls
2020-04-11EliminateTargetPaths: don't duplicate modules with only one instance (#1504)Albert Chen
* EliminateTargetPaths: add lone instance test cases * EliminateTargetPaths: don't rename lone instances * get rid of trailing comma Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-04-10Split Passes.scala into separate files (#1496)Adam Izraelevitz
* Split Passes.scala into separate files * Add imports of implicit things Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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