aboutsummaryrefslogtreecommitdiff
path: root/src/main/stanza
AgeCommit message (Collapse)Author
2016-02-24Fixed printf bugs in scala and stanza versions. Required special casing ↵Adam Izraelevitz
prints in SplitExp, and emitting expressions instead of their toString counterparts
2016-02-10Re-enable some passesPalmer Dabbelt
These were accidentally removed.
2016-02-09Merge branch 'master' of github.com:ucb-bar/firrtlazidar
2016-02-09Added license to FIRRTL filesazidar
2016-02-09Added chirrtl passes, need to update parserazidar
2016-02-09More bug fixesazidar
2016-02-09Added constprop,v-wrap,v-rename. All set to attempt like->like comparison of ↵azidar
rocketchip
2016-02-09Added Expand Whens passazidar
2016-02-09Moved check-high-form to operate on working irazidar
2016-02-09Changed stanza output of UInt/SInt to include widths. Made tests match ↵azidar
accordingly
2016-02-09Added remove accessesazidar
2016-02-09Added expand connect. Resolve now includes to working irazidar
2016-02-09WIP. Got to-working-ir workingazidar
2016-02-09WIP, nothing works. Starting creating working IR and necessary utilsazidar
2016-02-08Escape quotes in strings before emitting as VerilogPalmer Dabbelt
Without this we get failures with the current rocket-chip, when there are assertions with escaped strings in them.
2016-02-08Escape printf argument before emitting themPalmer Dabbelt
2016-01-28Fixed bug where subaccess indexes were being classified as female,azidar
mucking up the chirrtl->firrtl transform. #56.
2016-01-28Changed rmode to wmodeazidar
2016-01-28Use IsInvalid instead of Poisons in chirrtl -> firrtl transformazidar
2016-01-28Fixed bug where you cannot extract from a single bit wire in verilog. #55.azidar
2016-01-28Fixed bug where needed to cast bit-operation inputs prior to verilog emissionazidar
2016-01-28Added addw to working ir as an optimized verilog emissionazidar
2016-01-28Add map of symbol->symbol for wdefinstanceazidar
2016-01-28Fixed matching on types for and, or, and xorazidar
2016-01-28Fixed bug and updated test for changing mod to remazidar
2016-01-28Changed mod to remazidar
2016-01-28Updated with new primops. Removed addw,subw,quo,rem,bit. Added ↵azidar
head,tail,asClock.
2016-01-28Fixed readwriter syntax, and all printed mstats to use => instead of a colonazidar
2016-01-28Changed register syntax for optional reset and init valuesazidar
2016-01-27Reworked readwriter typesazidar
2016-01-27Fixed additional tests and inferring rdwr ports in chirrtljackkoenig
2016-01-25Fixed bug where poisons were not being declaredazidar
2016-01-25Added verilog rename passazidar
2016-01-25Added isinvalid and validifazidar
2016-01-25Removed println in expand whenazidar
2016-01-25Fixed width inference bug for muxesazidar
2016-01-25Removed random printlnazidar
2016-01-25Fixed support for muxes and nodes with passive aggregate typesazidar
2016-01-25Changed first generated name to use _0 postfixazidar
2016-01-24Made CInfer robust to high firrtl errorsazidar
2016-01-24Added muxing on passive aggregate typesazidar
2016-01-24Merge branch 'new-mem' of github.com:ucb-bar/firrtl into new-memazidar
2016-01-24Removed hashing as it made refchip slower to compileazidar
2016-01-24Added DefMemory to CInfer Typesazidar
2016-01-23Fix Verilog syntax errors for print/stopAndrew Waterman
2016-01-23Removed buggy optimization of dshr and dshlazidar
2016-01-23Moved inst declarations after other declarationsazidar
2016-01-23Fixed commas for instances in verilogazidar
2016-01-23Added more semicolonsazidar
2016-01-23Added semicolon after assigns in verilogazidar
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-30 14:44:18 +0000