| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2015-05-19 | Added support for non-inlined modules in verilog backend | azidar | |
| 2015-05-18 | First pass at a Verilog Backend. Not tested, but compiles and generates ↵ | azidar | |
| reasonable verilog. Requires inlining, future versions will instantiate modules | |||
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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