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path: root/src/main/stanza/verilog.stanza
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2016-01-16WIPazidar
2016-01-16WIP need to correctly output readwrite portsazidar
2016-01-16Printf no longer adds a new lineazidar
2016-01-16shift right does not cast input as signedazidar
2016-01-16Extraction inputs are no longer castazidar
2016-01-16Moved integer declaration inside module to be verilog (not system-verilog) ↵Adam Izraelevitz
compliant
2016-01-16Stop now emits correct verilog to stop simulation, required passing a string ↵azidar
not and integer
2016-01-16Fixed bug in printf and stop to correctly print to STDERRazidar
2016-01-16Finished adding clocks to Stop and Printazidar
2015-10-07Added Printf and Stop to firrtl. #23 #24.azidar
2015-10-06Merge pull request #45 from ucb-bar/change-mem-typeAdam Izraelevitz
Changed DefMemory to be a non-vector type with a size member
2015-10-01Changed DefMemory to be a non-vector type with a size member. Necessary for ↵azidar
ASIC backend.
2015-09-30Moved To-Real-Ir earlier, so CheckWidth could happen before PadWidthazidar
2015-08-26Fixed bug where subfields weren't entirely removedazidar
2015-08-25Fix Verilog backend for mixed signed-unsigned opsAndrew Waterman
Code like add(UInt<1>(1), SInt<1>(1)) was resulting in Verilog like $signed(1'h1) + $signed(1'sh1) which is incorrect: it computes -2, not 0. The fix is to zero-extend the unsigned operand, e.g. $signed({1'b0,1'h1}) + $signed(1'sh1)
2015-08-25Removed IntWidth, now only use LongWidth. Now do width inference for ↵azidar
Constants in parser, and correctly subtract 1 (except when 0) when calculating width from num-bits of BigInt
2015-08-20Added Poison node. Includes tests. #26.azidar
2015-08-18Fixed verilog emission from rand to randomazidar
2015-08-18Fixed so its length is greater than what it connects to. Changed shr to be ↵azidar
extract, not >>
2015-08-18Emit random initialization instead of zero initialization for Verilog regazidar
2015-08-17Added tests for shl and mem. Fixed bug in verilog output of mem size.azidar
2015-08-04Added verilog keywords to uniquify themazidar
2015-07-30Added module name to error messages.azidar
2015-07-30Added eqv for bitwise equality, and change eq to be arithmetic equalityazidar
2015-07-29Add bigint support.Adam Izraelevitz
2015-07-28Integrated bigint. Mostly works, but getting "cast" error for make Test.Adam Izraelevitz
2015-07-22Fixed verilog so it emits non-random inital values. Changed Not to beAdam Izraelevitz
correct.
2015-07-21Firrtl generates verilog that compiles, but does not workAdam Izraelevitz
2015-07-17Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog!Adam Izraelevitz
Had to separate initialization check pass Need to write dead code elimination pass Added LongWidth to support dshl that are huge
2015-07-16Merge branch 'new-low-firrtl' of github.com:ucb-bar/firrtl into new-low-firrtlazidar
Conflicts: src/main/stanza/firrtl-ir.stanza src/main/stanza/passes.stanza src/main/stanza/verilog.stanza
2015-07-14Fixed performance bug in backend. Added renamingazidar
2015-07-14Added tests for clocks. Added remove scope and special chars passes. Added ↵azidar
tests. Made more tests pass
2015-07-14Added clock supportazidar
2015-07-14Passes riscv-mini testsazidar
2015-07-14Still partial commit, many tests pass. Many tests fail.azidar
2015-07-14Partial commitazidar
2015-07-14In progress commitazidar
2015-07-13Added tests for clocks. Added remove scope and special chars passes. Added ↵azidar
tests. Made more tests pass
2015-07-10Added clock supportazidar
2015-07-07Passes riscv-mini testsazidar
2015-07-06Still partial commit, many tests pass. Many tests fail.azidar
2015-07-06Partial commitazidar
2015-07-06In progress commitazidar
2015-06-03Fixed verilog backend bugs. Passes ALU. Fails Datapathazidar
2015-06-02Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ↵azidar
low-firrtl syntax. Generates verilog that compiles, but is not correct
2015-06-02Added sequential/combinational memories. Started debugging verilog backend. ↵azidar
Added Long support so UInt(LARGENUMBER) works
2015-05-27Added sequential memories. mem no longer exists, must declare either cmem or ↵azidar
smem. Added firrtl-gensym utility to generate a hashmap of names
2015-05-27Added external modules. Switched lower firrtl back to wire r; r := Register, ↵azidar
instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed
2015-05-19Added support for non-inlined modules in verilog backendazidar
2015-05-18First pass at a Verilog Backend. Not tested, but compiles and generates ↵azidar
reasonable verilog. Requires inlining, future versions will instantiate modules
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