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path: root/src/main/stanza/verilog.stanza
AgeCommit message (Expand)Author
2015-07-21Firrtl generates verilog that compiles, but does not workAdam Izraelevitz
2015-07-17Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog!Adam Izraelevitz
2015-07-16Merge branch 'new-low-firrtl' of github.com:ucb-bar/firrtl into new-low-firrtlazidar
2015-07-14Fixed performance bug in backend. Added renamingazidar
2015-07-14Added tests for clocks. Added remove scope and special chars passes. Added te...azidar
2015-07-14Added clock supportazidar
2015-07-14Passes riscv-mini testsazidar
2015-07-14Still partial commit, many tests pass. Many tests fail.azidar
2015-07-14Partial commitazidar
2015-07-14In progress commitazidar
2015-07-13Added tests for clocks. Added remove scope and special chars passes. Added te...azidar
2015-07-10Added clock supportazidar
2015-07-07Passes riscv-mini testsazidar
2015-07-06Still partial commit, many tests pass. Many tests fail.azidar
2015-07-06Partial commitazidar
2015-07-06In progress commitazidar
2015-06-03Fixed verilog backend bugs. Passes ALU. Fails Datapathazidar
2015-06-02Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ...azidar
2015-06-02Added sequential/combinational memories. Started debugging verilog backend. A...azidar
2015-05-27Added sequential memories. mem no longer exists, must declare either cmem or ...azidar
2015-05-27Added external modules. Switched lower firrtl back to wire r; r := Register, ...azidar
2015-05-19Added support for non-inlined modules in verilog backendazidar
2015-05-18First pass at a Verilog Backend. Not tested, but compiles and generates reaso...azidar
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