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path: root/src/main/stanza/verilog.stanza
AgeCommit message (Expand)Author
2015-08-26Fixed bug where subfields weren't entirely removedazidar
2015-08-25Fix Verilog backend for mixed signed-unsigned opsAndrew Waterman
2015-08-25Removed IntWidth, now only use LongWidth. Now do width inference for Constant...azidar
2015-08-20Added Poison node. Includes tests. #26.azidar
2015-08-18Fixed verilog emission from rand to randomazidar
2015-08-18Fixed so its length is greater than what it connects to. Changed shr to be e...azidar
2015-08-18Emit random initialization instead of zero initialization for Verilog regazidar
2015-08-17Added tests for shl and mem. Fixed bug in verilog output of mem size.azidar
2015-08-04Added verilog keywords to uniquify themazidar
2015-07-30Added module name to error messages.azidar
2015-07-30Added eqv for bitwise equality, and change eq to be arithmetic equalityazidar
2015-07-29Add bigint support.Adam Izraelevitz
2015-07-28Integrated bigint. Mostly works, but getting "cast" error for make Test.Adam Izraelevitz
2015-07-22Fixed verilog so it emits non-random inital values. Changed Not to beAdam Izraelevitz
2015-07-21Firrtl generates verilog that compiles, but does not workAdam Izraelevitz
2015-07-17Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog!Adam Izraelevitz
2015-07-16Merge branch 'new-low-firrtl' of github.com:ucb-bar/firrtl into new-low-firrtlazidar
2015-07-14Fixed performance bug in backend. Added renamingazidar
2015-07-14Added tests for clocks. Added remove scope and special chars passes. Added te...azidar
2015-07-14Added clock supportazidar
2015-07-14Passes riscv-mini testsazidar
2015-07-14Still partial commit, many tests pass. Many tests fail.azidar
2015-07-14Partial commitazidar
2015-07-14In progress commitazidar
2015-07-13Added tests for clocks. Added remove scope and special chars passes. Added te...azidar
2015-07-10Added clock supportazidar
2015-07-07Passes riscv-mini testsazidar
2015-07-06Still partial commit, many tests pass. Many tests fail.azidar
2015-07-06Partial commitazidar
2015-07-06In progress commitazidar
2015-06-03Fixed verilog backend bugs. Passes ALU. Fails Datapathazidar
2015-06-02Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ...azidar
2015-06-02Added sequential/combinational memories. Started debugging verilog backend. A...azidar
2015-05-27Added sequential memories. mem no longer exists, must declare either cmem or ...azidar
2015-05-27Added external modules. Switched lower firrtl back to wire r; r := Register, ...azidar
2015-05-19Added support for non-inlined modules in verilog backendazidar
2015-05-18First pass at a Verilog Backend. Not tested, but compiles and generates reaso...azidar
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