| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-07-06 | Partial commit | azidar |
| 2015-07-06 | In progress commit | azidar |
| 2015-06-03 | Fixed verilog backend bugs. Passes ALU. Fails Datapath | azidar |
| 2015-06-02 | Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ... | azidar |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. A... | azidar |
| 2015-05-27 | Added sequential memories. mem no longer exists, must declare either cmem or ... | azidar |
| 2015-05-27 | Added external modules. Switched lower firrtl back to wire r; r := Register, ... | azidar |
| 2015-05-19 | Added support for non-inlined modules in verilog backend | azidar |
| 2015-05-18 | First pass at a Verilog Backend. Not tested, but compiles and generates reaso... | azidar |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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