| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-05-01 | Fixed bug where the enable was looked at for lowering MUX. | azidar |
| 2015-04-29 | Added dshl and dshr | azidar |
| 2015-04-24 | Fixed switch statement | azidar |
| 2015-04-24 | NEG now propogates input args plus one | azidar |
| 2015-04-24 | Updated TODO. Added backwards with prop for as and bits | azidar |
| 2015-04-24 | Incorrectly propagated width constraint for non-muxes. This is only true for ... | azidar |
| 2015-04-24 | Fixed width inference bug where later constraints on the output width were no... | azidar |
| 2015-04-22 | Switched to stricter primop width constraints. Implemented Pad. Added some mi... | azidar |
| 2015-04-17 | Removed excessive debug print statements, added default call to firrtl to gen... | azidar |
| 2015-04-17 | Fixed bug in primop lowering during type inference. Added reduce instructions... | azidar |
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
| aboutsummaryrefslogtreecommitdiff |