| Age | Commit message (Expand) | Author |
|---|
| 2016-01-28 | Changed rmode to wmode | azidar |
| 2016-01-28 | Fixed bug where you cannot extract from a single bit wire in verilog. #55. | azidar |
| 2016-01-28 | Fixed bug where needed to cast bit-operation inputs prior to verilog emission | azidar |
| 2016-01-28 | Added addw to working ir as an optimized verilog emission | azidar |
| 2016-01-28 | Add map of symbol->symbol for wdefinstance | azidar |
| 2016-01-28 | Changed mod to rem | azidar |
| 2016-01-28 | Updated with new primops. Removed addw,subw,quo,rem,bit. Added head,tail,asCl... | azidar |
| 2016-01-27 | Reworked readwriter types | azidar |
| 2016-01-25 | Fixed bug where poisons were not being declared | azidar |
| 2016-01-25 | Added verilog rename pass | azidar |
| 2016-01-25 | Added isinvalid and validif | azidar |
| 2016-01-25 | Removed println in expand when | azidar |
| 2016-01-25 | Fixed width inference bug for muxes | azidar |
| 2016-01-25 | Removed random println | azidar |
| 2016-01-25 | Fixed support for muxes and nodes with passive aggregate types | azidar |
| 2016-01-24 | Added muxing on passive aggregate types | azidar |
| 2016-01-24 | Merge branch 'new-mem' of github.com:ucb-bar/firrtl into new-mem | azidar |
| 2016-01-24 | Removed hashing as it made refchip slower to compile | azidar |
| 2016-01-24 | Added DefMemory to CInfer Types | azidar |
| 2016-01-23 | Fix Verilog syntax errors for print/stop | Andrew Waterman |
| 2016-01-23 | Removed buggy optimization of dshr and dshl | azidar |
| 2016-01-23 | Moved inst declarations after other declarations | azidar |
| 2016-01-23 | Fixed commas for instances in verilog | azidar |
| 2016-01-23 | Added more semicolons | azidar |
| 2016-01-23 | Added semicolon after assigns in verilog | azidar |
| 2016-01-23 | off by one error when emitting ports in verilog | azidar |
| 2016-01-23 | Fixed combinational read verilog backend | azidar |
| 2016-01-23 | Removed more prints ;) | azidar |
| 2016-01-23 | Fixed bug where the write mask wasn't being generated correctly | azidar |
| 2016-01-23 | Changed chirrtl to not require known mask values | azidar |
| 2016-01-20 | WIP, need to update chirrtl with new mask syntax | azidar |
| 2016-01-16 | Standard Verilog doesn't use Resolve(), but lists out the resolution passes i... | azidar |
| 2016-01-16 | Fixed bug in lowering memories that had aggregate data types | azidar |
| 2016-01-16 | Moved back to create-exps instead of fast-create-exps to fix bug - fast-creat... | azidar |
| 2016-01-16 | Reworked Verilog emission of registers to if/else instead of ?: | azidar |
| 2016-01-16 | No longer split on muxes | azidar |
| 2016-01-16 | Sped up remove access by checking a condition | azidar |
| 2016-01-16 | printf no longer includes a new line | azidar |
| 2016-01-16 | Verilog emission no longer casts input to shr or bit select | azidar |
| 2016-01-16 | Added hashed on get flip | azidar |
| 2016-01-16 | Sped up some passes. Added global mname to allow easy per-module hashes for a... | azidar |
| 2016-01-16 | Made create-exps a bit faster | azidar |
| 2016-01-16 | Fixed a bunch of tests, and minor bugs | azidar |
| 2016-01-16 | WIP Almost there, need to generate enable connections | azidar |
| 2016-01-16 | WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl... | azidar |
| 2016-01-16 | WIP getting through tests | azidar |
| 2016-01-16 | Finished supporting nested accesses. Required some nuianced thinking. Pass al... | azidar |
| 2016-01-16 | WIP, hit semantic bug in WSubAccess | azidar |
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar |
| 2016-01-16 | WIP. Compiles and almost done with verilog backend. Need to think about emitt... | azidar |
