| Age | Commit message (Expand) | Author |
|---|
| 2016-01-23 | Added more semicolons | azidar |
| 2016-01-23 | Added semicolon after assigns in verilog | azidar |
| 2016-01-23 | off by one error when emitting ports in verilog | azidar |
| 2016-01-23 | Fixed combinational read verilog backend | azidar |
| 2016-01-23 | Removed more prints ;) | azidar |
| 2016-01-23 | Fixed bug where the write mask wasn't being generated correctly | azidar |
| 2016-01-23 | Changed chirrtl to not require known mask values | azidar |
| 2016-01-20 | WIP, need to update chirrtl with new mask syntax | azidar |
| 2016-01-16 | Standard Verilog doesn't use Resolve(), but lists out the resolution passes i... | azidar |
| 2016-01-16 | Fixed bug in lowering memories that had aggregate data types | azidar |
| 2016-01-16 | Moved back to create-exps instead of fast-create-exps to fix bug - fast-creat... | azidar |
| 2016-01-16 | Reworked Verilog emission of registers to if/else instead of ?: | azidar |
| 2016-01-16 | No longer split on muxes | azidar |
| 2016-01-16 | Sped up remove access by checking a condition | azidar |
| 2016-01-16 | printf no longer includes a new line | azidar |
| 2016-01-16 | Verilog emission no longer casts input to shr or bit select | azidar |
| 2016-01-16 | Added hashed on get flip | azidar |
| 2016-01-16 | Sped up some passes. Added global mname to allow easy per-module hashes for a... | azidar |
| 2016-01-16 | Made create-exps a bit faster | azidar |
| 2016-01-16 | Fixed a bunch of tests, and minor bugs | azidar |
| 2016-01-16 | WIP Almost there, need to generate enable connections | azidar |
| 2016-01-16 | WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl... | azidar |
| 2016-01-16 | WIP getting through tests | azidar |
| 2016-01-16 | Finished supporting nested accesses. Required some nuianced thinking. Pass al... | azidar |
| 2016-01-16 | WIP, hit semantic bug in WSubAccess | azidar |
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar |
| 2016-01-16 | WIP. Compiles and almost done with verilog backend. Need to think about emitt... | azidar |
| 2016-01-16 | WIP. Compiles and there's some output | azidar |
| 2016-01-16 | WIP. Compiles, need to test | azidar |
| 2016-01-16 | WIP | azidar |
| 2016-01-16 | WIP need to correctly output readwrite ports | azidar |
| 2016-01-16 | Removed print statements | azidar |
| 2016-01-16 | Fixed inline-indexers bug where genders weren't properly calculated in | azidar |
| 2016-01-16 | Finished adding clocks to Stop and Print | azidar |
| 2015-11-02 | Deleted extranous passes.stanza comments, updated standard passes. Added supp... | jackkoenig |
| 2015-10-30 | Added support for -b <backend> so that specific passes can be run then a back... | jackkoenig |
| 2015-10-07 | Added Printf and Stop to firrtl. #23 #24. | azidar |
| 2015-10-06 | Merge pull request #45 from ucb-bar/change-mem-type | Adam Izraelevitz |
| 2015-10-01 | Merge pull request #43 from ucb-bar/new-semantics | Andrew Waterman |
| 2015-10-01 | Changed DefMemory to be a non-vector type with a size member. Necessary for A... | azidar |
| 2015-10-01 | Change of FIRRTL semantics! | azidar |
| 2015-09-30 | Moved To-Real-Ir earlier, so CheckWidth could happen before PadWidth | azidar |
| 2015-09-30 | Fixed naming bug where __1 was matching. Caused lots o issues. | azidar |
| 2015-09-29 | Fixed final bug. All tests pass. Accessors are a go. | azidar |
| 2015-09-29 | Added DecToIndexer/DecFromIndexer. Fixed most use cases of incorrect catching... | azidar |
| 2015-08-28 | Moved check type and check kind after check gender | azidar |
| 2015-08-26 | Fixed bug where firrtl was incorrectly judging the width of a bigint. #36 #37. | azidar |
| 2015-08-25 | Fixed bug in split expression that leaked connect statements out of a conditi... | azidar |
| 2015-08-25 | Removed IntWidth, now only use LongWidth. Now do width inference for Constant... | azidar |
| 2015-08-25 | Added width check pass with tests. #22. | azidar |
