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path: root/src/main/stanza/passes.stanza
AgeCommit message (Expand)Author
2016-01-16WIP. Compiles and there's some outputazidar
2016-01-16WIP. Compiles, need to testazidar
2016-01-16WIPazidar
2016-01-16WIP need to correctly output readwrite portsazidar
2016-01-16Removed print statementsazidar
2016-01-16Fixed inline-indexers bug where genders weren't properly calculated inazidar
2016-01-16Finished adding clocks to Stop and Printazidar
2015-11-02Deleted extranous passes.stanza comments, updated standard passes. Added supp...jackkoenig
2015-10-30Added support for -b <backend> so that specific passes can be run then a back...jackkoenig
2015-10-07Added Printf and Stop to firrtl. #23 #24.azidar
2015-10-06Merge pull request #45 from ucb-bar/change-mem-typeAdam Izraelevitz
2015-10-01Merge pull request #43 from ucb-bar/new-semanticsAndrew Waterman
2015-10-01Changed DefMemory to be a non-vector type with a size member. Necessary for A...azidar
2015-10-01Change of FIRRTL semantics!azidar
2015-09-30Moved To-Real-Ir earlier, so CheckWidth could happen before PadWidthazidar
2015-09-30Fixed naming bug where __1 was matching. Caused lots o issues.azidar
2015-09-29Fixed final bug. All tests pass. Accessors are a go.azidar
2015-09-29Added DecToIndexer/DecFromIndexer. Fixed most use cases of incorrect catching...azidar
2015-08-28Moved check type and check kind after check genderazidar
2015-08-26Fixed bug where firrtl was incorrectly judging the width of a bigint. #36 #37.azidar
2015-08-25Fixed bug in split expression that leaked connect statements out of a conditi...azidar
2015-08-25Removed IntWidth, now only use LongWidth. Now do width inference for Constant...azidar
2015-08-25Added width check pass with tests. #22.azidar
2015-08-20Added Poison node. Includes tests. #26.azidar
2015-08-20Added rsh to BigInt library. Const Prop now works on rsh's on constants. #19.azidar
2015-08-20Fixed bigint library to correctly extract bits from UIntValue. #19.azidar
2015-08-19Added beginning of constant propagation pass, doesn't workazidar
2015-08-19Switched to new bigint libraryazidar
2015-08-19Fixed width inference bug where constraints were propagating backwards.azidar
2015-08-18Fixed width inference for static shift left, #18azidar
2015-08-18Fixed bug in MinusWidth where it was adding instead of subtracting widthsazidar
2015-08-17Fixed bug where equality between expressions was incorrect, leading toazidar
2015-08-05Fixed bug in temp elimination.azidar
2015-08-04Added check for reading from outputs with flipsazidar
2015-08-04Added () around width printersazidar
2015-08-04Added verilog keywords to uniquify themazidar
2015-08-03Changed name mangling to use _ as a delin. Fixed bug in checking forazidar
2015-08-03Fixed performance bug in Split Expressions. Changed delin for connect indexed...azidar
2015-07-30Added module name to error messages.azidar
2015-07-30Updated error and feature tests. Fixed bug in detecting incorrect gendersazidar
2015-07-30Added eqv for bitwise equality, and change eq to be arithmetic equalityazidar
2015-07-30Updated lots of tests so they pass. Found one bug in expand whensazidar
2015-07-29Finished supporting Chisel 2.0 Ref ChipAdam Izraelevitz
2015-07-28Integrated bigint. Mostly works, but getting "cast" error for make Test.Adam Izraelevitz
2015-07-21Fixed bug in fix :Pazidar
2015-07-21Fixed removing non-referenced componentsazidar
2015-07-21Made things go faster. Still in progress. Expand when now removesAdam Izraelevitz
2015-07-17Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog!Adam Izraelevitz
2015-07-16Fixed rename to work with chisel3 stuffazidar
2015-07-14Fixed performance bug in backend. Added renamingazidar
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