| Age | Commit message (Expand) | Author |
|---|
| 2015-08-28 | Moved check type and check kind after check gender | azidar |
| 2015-08-26 | Fixed bug where firrtl was incorrectly judging the width of a bigint. #36 #37. | azidar |
| 2015-08-25 | Fixed bug in split expression that leaked connect statements out of a conditi... | azidar |
| 2015-08-25 | Removed IntWidth, now only use LongWidth. Now do width inference for Constant... | azidar |
| 2015-08-25 | Added width check pass with tests. #22. | azidar |
| 2015-08-20 | Added Poison node. Includes tests. #26. | azidar |
| 2015-08-20 | Added rsh to BigInt library. Const Prop now works on rsh's on constants. #19. | azidar |
| 2015-08-20 | Fixed bigint library to correctly extract bits from UIntValue. #19. | azidar |
| 2015-08-19 | Added beginning of constant propagation pass, doesn't work | azidar |
| 2015-08-19 | Switched to new bigint library | azidar |
| 2015-08-19 | Fixed width inference bug where constraints were propagating backwards. | azidar |
| 2015-08-18 | Fixed width inference for static shift left, #18 | azidar |
| 2015-08-18 | Fixed bug in MinusWidth where it was adding instead of subtracting widths | azidar |
| 2015-08-17 | Fixed bug where equality between expressions was incorrect, leading to | azidar |
| 2015-08-05 | Fixed bug in temp elimination. | azidar |
| 2015-08-04 | Added check for reading from outputs with flips | azidar |
| 2015-08-04 | Added () around width printers | azidar |
| 2015-08-04 | Added verilog keywords to uniquify them | azidar |
| 2015-08-03 | Changed name mangling to use _ as a delin. Fixed bug in checking for | azidar |
| 2015-08-03 | Fixed performance bug in Split Expressions. Changed delin for connect indexed... | azidar |
| 2015-07-30 | Added module name to error messages. | azidar |
| 2015-07-30 | Updated error and feature tests. Fixed bug in detecting incorrect genders | azidar |
| 2015-07-30 | Added eqv for bitwise equality, and change eq to be arithmetic equality | azidar |
| 2015-07-30 | Updated lots of tests so they pass. Found one bug in expand whens | azidar |
| 2015-07-29 | Finished supporting Chisel 2.0 Ref Chip | Adam Izraelevitz |
| 2015-07-28 | Integrated bigint. Mostly works, but getting "cast" error for make Test. | Adam Izraelevitz |
| 2015-07-21 | Fixed bug in fix :P | azidar |
| 2015-07-21 | Fixed removing non-referenced components | azidar |
| 2015-07-21 | Made things go faster. Still in progress. Expand when now removes | Adam Izraelevitz |
| 2015-07-17 | Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog! | Adam Izraelevitz |
| 2015-07-16 | Fixed rename to work with chisel3 stuff | azidar |
| 2015-07-14 | Fixed performance bug in backend. Added renaming | azidar |
| 2015-07-14 | Added tests for clocks. Added remove scope and special chars passes. Added te... | azidar |
| 2015-07-14 | Added clock support | azidar |
| 2015-07-14 | Updated flo backend | azidar |
| 2015-07-14 | Passes riscv-mini tests | azidar |
| 2015-07-14 | Pass most tests. The ones that do not pass are not expected to, yet | azidar |
| 2015-07-14 | Still partial commit, many tests pass. Many tests fail. | azidar |
| 2015-07-14 | In progress commit | azidar |
| 2015-07-14 | Fixed bug in lowering, where the indexes to many-connects and accessors weren... | azidar |
| 2015-07-06 | Updated todo | azidar |
| 2015-07-01 | Updated TODO. | azidar |
| 2015-06-12 | Major revisions to spec. Bumped to v0.1.2 | azidar |
| 2015-06-02 | Added low firrtl check. Corrected bug in prefix matching in high firrtl check | azidar |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. A... | azidar |
| 2015-05-27 | Added sequential memories. mem no longer exists, must declare either cmem or ... | azidar |
| 2015-05-27 | Added external modules. Switched lower firrtl back to wire r; r := Register, ... | azidar |
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar |
| 2015-05-20 | Added Pad pass to flo.stanza, which pads widths to make := and primops strict... | azidar |
| 2015-05-19 | Merge pull request #8 from jackbackrack/master | Adam Izraelevitz |
