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path: root/src/main/stanza/ir-utils.stanza
AgeCommit message (Expand)Author
2016-01-16WIP need to correctly output readwrite portsazidar
2016-01-16Finished adding clocks to Stop and Printazidar
2015-10-30Added support for -b <backend> so that specific passes can be run then a back...jackkoenig
2015-10-14Don't emit SystemVerilog keywordsAndrew Waterman
2015-10-07Added Printf and Stop to firrtl. #23 #24.azidar
2015-10-06Merge pull request #45 from ucb-bar/change-mem-typeAdam Izraelevitz
2015-10-01Changed DefMemory to be a non-vector type with a size member. Necessary for A...azidar
2015-09-30Fixed naming bug where __1 was matching. Caused lots o issues.azidar
2015-08-26Fixed bug where firrtl was incorrectly judging the width of a bigint. #36 #37.azidar
2015-08-25Removed IntWidth, now only use LongWidth. Now do width inference for Constant...azidar
2015-08-20Added Poison node. Includes tests. #26.azidar
2015-08-20Added rsh to BigInt library. Const Prop now works on rsh's on constants. #19.azidar
2015-08-19Switched to new bigint libraryazidar
2015-08-04Added verilog keywords to uniquify themazidar
2015-08-04Fixed reading from instance's input ports. Fixed unique naming bug.azidar
2015-08-03Changed name mangling to use _ as a delin. Fixed bug in checking forazidar
2015-08-03Fixed performance bug in Split Expressions. Changed delin for connect indexed...azidar
2015-07-30Added module name to error messages.azidar
2015-07-30Added eqv for bitwise equality, and change eq to be arithmetic equalityazidar
2015-07-30Updated lots of tests so they pass. Found one bug in expand whensazidar
2015-07-21Made things go faster. Still in progress. Expand when now removesAdam Izraelevitz
2015-07-17Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog!Adam Izraelevitz
2015-07-14Added clock supportazidar
2015-07-14Still partial commit, many tests pass. Many tests fail.azidar
2015-07-14In progress commitazidar
2015-07-02Fixed performance bugs, runs 7x fasterazidar
2015-06-02Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ...azidar
2015-06-02Added sequential/combinational memories. Started debugging verilog backend. A...azidar
2015-05-27Added sequential memories. mem no longer exists, must declare either cmem or ...azidar
2015-05-27Added external modules. Switched lower firrtl back to wire r; r := Register, ...azidar
2015-05-26Added <>. Added additional checks for primops. Added new chisel3 files.azidar
2015-05-18Big API Change. Pad is no longer supported. Widths of primops can be flexible...azidar
2015-05-15Updated firrtl for its passes to be a bit more modular, and to enable pluggin...azidar
2015-05-13Added source indicators from FIRRTL files. Pass in -p i to get them printed. ...azidar
2015-04-29Added dshl and dshrazidar
2015-04-27Added on-resetazidar
2015-04-24Merge branch 'master' of github.com:ucb-bar/firrtl into parserazidar
2015-04-23Fixed bug in lowering where the arguments to DoPrim and Pad weren't loweredazidar
2015-04-23Fixed bug in map where mems were mysteriously turning into regsazidar
2015-04-23Not finished commmitazidar
2015-04-23Added new parser. Fixed all Tests. Added on-reset to parser, but don't correc...azidar
2015-04-22Switched to stricter primop width constraints. Implemented Pad. Added some mi...azidar
2015-04-20Fixed tests to use new execution arguments. Added and fixed chisel3 bugsazidar
2015-04-17Fixed bug in primop lowering during type inference. Added reduce instructions...azidar
2015-04-16Updated parser to correctly read empty statementsazidar
2015-04-16Merged with new stanzaazidar
2015-04-13Finished Infer Widthsazidar
2015-04-10Almost finished width inference, takes too long/infinite loop for gcdazidar
2015-04-10Updated StanzaPatrick Li
2015-04-09Added more 'fake' tests. infer-widths now collects constraintsazidar
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