| Age | Commit message (Expand) | Author |
|---|
| 2016-01-16 | WIP. Compiles, need to test | azidar |
| 2016-01-16 | WIP | azidar |
| 2016-01-16 | Finished adding clocks to Stop and Print | azidar |
| 2015-10-07 | Added Printf and Stop to firrtl. #23 #24. | azidar |
| 2015-10-01 | Changed DefMemory to be a non-vector type with a size member. Necessary for A... | azidar |
| 2015-08-26 | Fixed bug where firrtl was incorrectly judging the width of a bigint. #36 #37. | azidar |
| 2015-08-25 | Removed IntWidth, now only use LongWidth. Now do width inference for Constant... | azidar |
| 2015-08-20 | Added Poison node. Includes tests. #26. | azidar |
| 2015-08-20 | Added rsh to BigInt library. Const Prop now works on rsh's on constants. #19. | azidar |
| 2015-08-19 | Switched to new bigint library | azidar |
| 2015-08-19 | Check Neg UInt in the parser | azidar |
| 2015-08-03 | Added concrete syntax for EmptyStmt() | azidar |
| 2015-07-30 | Added eqv for bitwise equality, and change eq to be arithmetic equality | azidar |
| 2015-07-30 | Updated lots of tests so they pass. Found one bug in expand whens | azidar |
| 2015-07-29 | Finished supporting Chisel 2.0 Ref Chip | Adam Izraelevitz |
| 2015-07-29 | Add bigint support. | Adam Izraelevitz |
| 2015-07-28 | Integrated bigint. Mostly works, but getting "cast" error for make Test. | Adam Izraelevitz |
| 2015-07-21 | Made things go faster. Still in progress. Expand when now removes | Adam Izraelevitz |
| 2015-07-17 | Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog! | Adam Izraelevitz |
| 2015-07-14 | Added clock support | azidar |
| 2015-07-14 | Still partial commit, many tests pass. Many tests fail. | azidar |
| 2015-07-14 | In progress commit | azidar |
| 2015-07-02 | Fixed stanza, optimize works, added a time printout | azidar |
| 2015-07-02 | Hopefully fixed stanza so it can correctly compile itself | azidar |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. A... | azidar |
| 2015-05-27 | Added sequential memories. mem no longer exists, must declare either cmem or ... | azidar |
| 2015-05-27 | Added external modules. Switched lower firrtl back to wire r; r := Register, ... | azidar |
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar |
| 2015-05-18 | Big API Change. Pad is no longer supported. Widths of primops can be flexible... | azidar |
| 2015-05-13 | Added source indicators from FIRRTL files. Pass in -p i to get them printed. ... | azidar |
| 2015-04-29 | Added dshl and dshr | azidar |
| 2015-04-27 | Added on-reset | azidar |
| 2015-04-23 | Not finished commmit | azidar |
| 2015-04-23 | Added new parser. Fixed all Tests. Added on-reset to parser, but don't correc... | azidar |
| 2015-04-22 | Switched to stricter primop width constraints. Implemented Pad. Added some mi... | azidar |
| 2015-04-17 | Removed excessive debug print statements, added default call to firrtl to gen... | azidar |
| 2015-04-17 | Fixed bug in primop lowering during type inference. Added reduce instructions... | azidar |
| 2015-04-16 | Updated parser to correctly read empty statements | azidar |
| 2015-04-16 | Merged with new stanza | azidar |
| 2015-04-15 | Finished flo backend. Restructured todo list | azidar |
| 2015-04-10 | Updated Stanza | Patrick Li |
| 2015-04-09 | Added more 'fake' tests. infer-widths now collects constraints | azidar |
| 2015-03-25 | Correctly do when expansion, minus enables and outputting lowered form | azidar |
| 2015-03-24 | Changed PrimOp to interface | Patrick Li |
| 2015-03-24 | Fixed minor bugs, but looks like there is a stanza bug. This blows. And sucks. | azidar |
| 2015-03-24 | With new stanza | azidar |
| 2015-03-12 | Switched bundles from gender to flip | azidar |
| 2015-03-11 | Finished expand accessors pass. Fixed bug in resolve-gender. Added tests, all... | azidar |
| 2015-03-05 | Finished part of infer gender, tests not committed | azidar |
| 2015-03-04 | Changed lots of directions to genders. Started writing infer-gender pass. Doe... | azidar |
