sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2015-06-04	Fixed fir files so they correctly compile to verilog! Front-end needs to gene...	azidar
2015-06-02	Changed Core.fir so dshl wasn't huge. Fixed padding pass to preserve correct ...	azidar
2015-06-02	merge + fix trim to use correct bits operands	jackbackrack
2015-05-29	fix concat, as-sint, turn off temp-elimination	jackbackrack
2015-05-27	Added sequential memories. mem no longer exists, must declare either cmem or ...	azidar
2015-05-27	Added external modules. Switched lower firrtl back to wire r; r := Register, ...	azidar
2015-05-21	fix pad/trim pass and fix bug in bits-select width inference	jackbackrack
2015-05-21	Added pad pass, used for flo backend	azidar
2015-05-20	Merge branch 'master' of github.com:ucb-bar/firrtl	azidar
2015-05-20	fix writeport emission for flo	jackbackrack
2015-05-20	Added Pad pass to flo.stanza, which pads widths to make := and primops strict...	azidar
2015-05-19	get flo backend running again with no pads and generic operators	jackbackrack
2015-05-18	Big API Change. Pad is no longer supported. Widths of primops can be flexible...	azidar
2015-05-15	Updated firrtl for its passes to be a bit more modular, and to enable pluggin...	azidar