sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2015-07-14	Updated flo backend	azidar
2015-07-14	Still partial commit, many tests pass. Many tests fail.	azidar
2015-07-02	Hopefully fixed stanza so it can correctly compile itself	azidar
2015-05-29	Fixed bugs in when-coverage pass. Works but has not been thoroughly tested	azidar
2015-05-29	Added custom pass. Does not correctly run, stanza just spins. Requires debugg...	azidar
2015-05-18	First pass at a Verilog Backend. Not tested, but compiles and generates reaso...	azidar
2015-05-18	Big API Change. Pad is no longer supported. Widths of primops can be flexible...	azidar
2015-05-15	Updated firrtl for its passes to be a bit more modular, and to enable pluggin...	azidar
2015-05-13	Added source indicators from FIRRTL files. Pass in -p i to get them printed. ...	azidar
2015-05-02	Added a infrastructure for check passes, and wrote a few	azidar
2015-04-22	Switched to stricter primop width constraints. Implemented Pad. Added some mi...	azidar
2015-04-20	Fixed tests to use new execution arguments. Added and fixed chisel3 bugs	azidar
2015-04-17	Removed excessive debug print statements, added default call to firrtl to gen...	azidar
2015-04-17	Fixed bug in primop lowering during type inference. Added reduce instructions...	azidar
2015-04-10	Updated Stanza	Patrick Li
2015-04-08	Finished expand whens. started infer widths. added pdf for people to view	azidar
2015-03-24	With new stanza	azidar
2015-03-04	Changed lots of directions to genders. Started writing infer-gender pass. Doe...	azidar
2015-02-25	Added debug print statements to dump fields from nodes, and updated tests to ...	azidar
2015-02-24	Rewrote README to include installation instructions and stanza justification....	azidar