sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2016-01-25	Added isinvalid and validif	azidar

2016-01-24	Added muxing on passive aggregate types	azidar

2016-01-23	Added prefix checker, now compliant with firrtl spec	azidar

2016-01-23	Changed chirrtl to not require known mask values	azidar

2016-01-20	WIP, need to update chirrtl with new mask syntax	azidar

2016-01-17	Forgot to add the changes	azidar

2016-01-17	BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed tests	azidar

2016-01-16	Fixed bug in check-init that allows it to check on non-lowered things	azidar

2016-01-16	Nodes must now be ground types	azidar

2016-01-16	Sped up some passes. Added global mname to allow easy per-module hashes for ↵	azidar
	accellerating functions
2016-01-16	Fixed a bunch of tests, and minor bugs	azidar

2016-01-16	WIP, hit semantic bug in WSubAccess	azidar

2016-01-16	WIP	azidar

2015-10-07	Added Printf and Stop to firrtl. #23 #24.	azidar

2015-10-01	Changed DefMemory to be a non-vector type with a size member. Necessary for ↵	azidar
	ASIC backend.
2015-08-31	Sped up low form check by not checking the type of every expression, as it ↵	azidar
	is unneeded
2015-08-28	Moved check type and check kind after check gender	azidar

2015-08-26	Fixed bug where firrtl was incorrectly judging the width of a bigint. #36 #37.	azidar

2015-08-25	Removed IntWidth, now only use LongWidth. Now do width inference for ↵	azidar
	Constants in parser, and correctly subtract 1 (except when 0) when calculating width from num-bits of BigInt
2015-08-25	Added width check pass with tests. #22.	azidar

2015-08-20	Added tests, cleaned up repo	azidar

2015-08-20	Added Poison node. Includes tests. #26.	azidar

2015-08-19	Check Neg UInt in the parser	azidar

2015-08-04	Added check for reading from outputs with flips	azidar

2015-08-04	Fixed reading from instance's input ports. Fixed unique naming bug.	azidar

2015-08-03	Changed name mangling to use _ as a delin. Fixed bug in checking for	azidar
	invalid <> assignments.
2015-07-31	Fixed (?) resolve genders pass	azidar

2015-07-31	Reading from output ports no longer causes errors	azidar

2015-07-31	Allow bit operations on sints	azidar

2015-07-31	Added errors for bulk connects where field names match but types/flips don't	azidar

2015-07-30	Added module name to error messages.	azidar

2015-07-30	Updated error and feature tests. Fixed bug in detecting incorrect genders	azidar

2015-07-30	Added eqv for bitwise equality, and change eq to be arithmetic equality	azidar

2015-07-29	Finished supporting Chisel 2.0 Ref Chip	Adam Izraelevitz

2015-07-28	Integrated bigint. Mostly works, but getting "cast" error for make Test.	Adam Izraelevitz

2015-07-21	Made things go faster. Still in progress. Expand when now removes	Adam Izraelevitz
	non-referenced declarations that are not instances, but it doesn't work right now.
2015-07-17	Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog!	Adam Izraelevitz
	Had to separate initialization check pass Need to write dead code elimination pass Added LongWidth to support dshl that are huge
2015-07-14	Fixed performance bug in backend. Added renaming	azidar

2015-07-14	Added tests for clocks. Added remove scope and special chars passes. Added ↵	azidar
	tests. Made more tests pass
2015-07-14	Added clock support	azidar

2015-07-14	Still partial commit, many tests pass. Many tests fail.	azidar

2015-07-14	In progress commit	azidar

2015-07-06	Updated todo	azidar

2015-07-02	Fixed performance bugs, runs 7x faster	azidar

2015-06-02	Added low firrtl check. Corrected bug in prefix matching in high firrtl check	azidar

2015-06-02	Added sequential/combinational memories. Started debugging verilog backend. ↵	azidar
	Added Long support so UInt(LARGENUMBER) works
2015-05-27	Added external modules. Switched lower firrtl back to wire r; r := Register, ↵	azidar
	instead of using nodes. Added a renaming pass for different backends. This will likely get deprecated, as a more robust name mangling scheme could be needed
2015-05-26	Added <>. Added additional checks for primops. Added new chisel3 files.	azidar

2015-05-19	get flo backend running again with no pads and generic operators	jackbackrack

2015-05-18	get coercion running for flo backend and disable negative lit check	jackbackrack