| Age | Commit message (Expand) | Author |
|---|
| 2016-01-16 | WIP, hit semantic bug in WSubAccess | azidar |
| 2016-01-16 | WIP | azidar |
| 2015-10-07 | Added Printf and Stop to firrtl. #23 #24. | azidar |
| 2015-10-01 | Changed DefMemory to be a non-vector type with a size member. Necessary for A... | azidar |
| 2015-08-31 | Sped up low form check by not checking the type of every expression, as it is... | azidar |
| 2015-08-28 | Moved check type and check kind after check gender | azidar |
| 2015-08-26 | Fixed bug where firrtl was incorrectly judging the width of a bigint. #36 #37. | azidar |
| 2015-08-25 | Removed IntWidth, now only use LongWidth. Now do width inference for Constant... | azidar |
| 2015-08-25 | Added width check pass with tests. #22. | azidar |
| 2015-08-20 | Added tests, cleaned up repo | azidar |
| 2015-08-20 | Added Poison node. Includes tests. #26. | azidar |
| 2015-08-19 | Check Neg UInt in the parser | azidar |
| 2015-08-04 | Added check for reading from outputs with flips | azidar |
| 2015-08-04 | Fixed reading from instance's input ports. Fixed unique naming bug. | azidar |
| 2015-08-03 | Changed name mangling to use _ as a delin. Fixed bug in checking for | azidar |
| 2015-07-31 | Fixed (?) resolve genders pass | azidar |
| 2015-07-31 | Reading from output ports no longer causes errors | azidar |
| 2015-07-31 | Allow bit operations on sints | azidar |
| 2015-07-31 | Added errors for bulk connects where field names match but types/flips don't | azidar |
| 2015-07-30 | Added module name to error messages. | azidar |
| 2015-07-30 | Updated error and feature tests. Fixed bug in detecting incorrect genders | azidar |
| 2015-07-30 | Added eqv for bitwise equality, and change eq to be arithmetic equality | azidar |
| 2015-07-29 | Finished supporting Chisel 2.0 Ref Chip | Adam Izraelevitz |
| 2015-07-28 | Integrated bigint. Mostly works, but getting "cast" error for make Test. | Adam Izraelevitz |
| 2015-07-21 | Made things go faster. Still in progress. Expand when now removes | Adam Izraelevitz |
| 2015-07-17 | Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog! | Adam Izraelevitz |
| 2015-07-14 | Fixed performance bug in backend. Added renaming | azidar |
| 2015-07-14 | Added tests for clocks. Added remove scope and special chars passes. Added te... | azidar |
| 2015-07-14 | Added clock support | azidar |
| 2015-07-14 | Still partial commit, many tests pass. Many tests fail. | azidar |
| 2015-07-14 | In progress commit | azidar |
| 2015-07-06 | Updated todo | azidar |
| 2015-07-02 | Fixed performance bugs, runs 7x faster | azidar |
| 2015-06-02 | Added low firrtl check. Corrected bug in prefix matching in high firrtl check | azidar |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. A... | azidar |
| 2015-05-27 | Added external modules. Switched lower firrtl back to wire r; r := Register, ... | azidar |
| 2015-05-26 | Added <>. Added additional checks for primops. Added new chisel3 files. | azidar |
| 2015-05-19 | get flo backend running again with no pads and generic operators | jackbackrack |
| 2015-05-18 | get coercion running for flo backend and disable negative lit check | jackbackrack |
| 2015-05-18 | Big API Change. Pad is no longer supported. Widths of primops can be flexible... | azidar |
| 2015-05-15 | Updated firrtl for its passes to be a bit more modular, and to enable pluggin... | azidar |
| 2015-05-13 | Added source indicators from FIRRTL files. Pass in -p i to get them printed. ... | azidar |
| 2015-05-13 | Updated Spec. Added scoped-reg which exposes on-reset bug. Fixed lowering bug | azidar |
| 2015-05-05 | Added a bunch of tests. In the middle of implementing check kinds and check t... | azidar |
| 2015-05-04 | Updated stuff | azidar |
| 2015-05-04 | Added a few more error checks. Not tested yet. Fixed bug in pad type inference | azidar |
| 2015-05-02 | Added a infrastructure for check passes, and wrote a few | azidar |
