| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-07-14 | Added clock support | azidar |
| 2015-06-03 | Fixed verilog backend bugs. Passes ALU. Fails Datapath | azidar |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. A... | azidar |
| 2015-05-29 | Fixed bugs in when-coverage pass. Works but has not been thoroughly tested | azidar |
| 2015-05-29 | Added custom pass. Does not correctly run, stanza just spins. Requires debugg... | azidar |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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