| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-06-02 | merge + fix trim to use correct bits operands | jackbackrack |
| 2015-05-29 | fix concat, as-sint, turn off temp-elimination | jackbackrack |
| 2015-05-27 | Added external modules. Switched lower firrtl back to wire r; r := Register, ... | azidar |
| 2015-05-20 | Added Pad pass to flo.stanza, which pads widths to make := and primops strict... | azidar |
| 2015-05-19 | Added support for non-inlined modules in verilog backend | azidar |
| 2015-05-18 | First pass at a Verilog Backend. Not tested, but compiles and generates reaso... | azidar |
| 2015-05-15 | Updated firrtl for its passes to be a bit more modular, and to enable pluggin... | azidar |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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