| Age | Commit message (Expand) | Author |
|---|
| 2015-07-30 | Added module name to error messages. | azidar |
| 2015-07-21 | Firrtl generates verilog that compiles, but does not work | Adam Izraelevitz |
| 2015-07-21 | Fixed bug in fix :P | azidar |
| 2015-07-21 | Fixed removing non-referenced components | azidar |
| 2015-07-21 | Made things go faster. Still in progress. Expand when now removes | Adam Izraelevitz |
| 2015-07-17 | Datapath compiles with Chisel 2.0 -> FIRRTL -> Verilog! | Adam Izraelevitz |
| 2015-07-16 | Fixed rename to work with chisel3 stuff | azidar |
| 2015-07-14 | Fixed performance bug in backend. Added renaming | azidar |
| 2015-07-14 | Added tests for clocks. Added remove scope and special chars passes. Added te... | azidar |
| 2015-07-14 | Added clock support | azidar |
| 2015-07-14 | Updated flo backend | azidar |
| 2015-07-14 | Still partial commit, many tests pass. Many tests fail. | azidar |
| 2015-07-02 | Fixed stanza, optimize works, added a time printout | azidar |
| 2015-06-03 | Fixed verilog backend bugs. Passes ALU. Fails Datapath | azidar |
| 2015-06-02 | Added low firrtl check. Corrected bug in prefix matching in high firrtl check | azidar |
| 2015-06-02 | Merge branch 'master' of github.com:ucb-bar/firrtl | azidar |
| 2015-06-02 | Added sequential/combinational memories. Started debugging verilog backend. A... | azidar |
| 2015-06-02 | turn off eliminate-temps until improved | jackbackrack |
| 2015-06-02 | merge + fix trim to use correct bits operands | jackbackrack |
| 2015-05-29 | fix concat, as-sint, turn off temp-elimination | jackbackrack |
| 2015-05-27 | Added external modules. Switched lower firrtl back to wire r; r := Register, ... | azidar |
| 2015-05-20 | Added Pad pass to flo.stanza, which pads widths to make := and primops strict... | azidar |
| 2015-05-19 | Added support for non-inlined modules in verilog backend | azidar |
| 2015-05-18 | First pass at a Verilog Backend. Not tested, but compiles and generates reaso... | azidar |
| 2015-05-15 | Updated firrtl for its passes to be a bit more modular, and to enable pluggin... | azidar |
