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AgeCommit message (Collapse)Author
2016-05-24Added Errors class and fixed tests.azidar
Canonicalizes catching/throwing PassExceptions.
2016-05-24add better type mismatch error messageColin Schmidt
also check for it int unittest
2016-05-24Remove nested AND in creation of readwrite ports for mems.jackkoenig
Fixes #147
2016-05-24Fix LowerTypes to check for wmode instead of rmodejackkoenig
2016-05-12Restructured Compiler to use Transforms. Added an InlineInstance pass.Adam Izraelevitz
Transforms are new unit of modularity within the compiler.
2016-05-12Implement File Infojackkoenig
2016-05-11Remove trait StanzaPass and related dead codejackkoenig
2016-05-10Remove old SplitExp pass (replaced by SplitExpressions)jackkoenig
2016-05-10Modified Verilog compiler to use new passesAdam Izraelevitz
RemoveValidIf, SplitExpressions, and PadWidths
2016-05-10Added RemoveValidIf pass.Adam Izraelevitz
This is to start moving stuff out of Emitter and into separate passes
2016-05-10Added new (and correct) Split Expressions passAdam Izraelevitz
2016-05-10Added pad widths to eliminate all implicit width extendingAdam Izraelevitz
2016-05-10Added constant propagation rule for greater/less thansAdam Izraelevitz
2016-05-10Fixed emission of memory ports to all be in the same always @ clock.Adam Izraelevitz
Changed initialization to assign the correct number of random bits.
2016-05-03Remove line in Verilog Emitter erroneously printing ); before module defjackkoenig
Fixes #133
2016-05-03Refactor Check Initialization to trace voids through temporary nodesjackkoenig
2016-05-03Make style and spacing of Check Initialization more idiomatic Scalajackkoenig
2016-05-03Move Check Initialization to its own filejackkoenig
2016-05-03Rewrite ExpandWhens to memoize complex default valuesjackkoenig
Fixes #113 and Fixes #150
2016-05-03Change style and spacing of Expand Whens to be more idiomatic Scalajackkoenig
2016-05-03Move ExpandWhens to its own filejackkoenig
2016-05-03Add Utils function getDeclarationjackkoenig
2016-05-03Move splitRef and mergeRef from LowerTypes to Utilsjackkoenig
Make EmptyExpression part of WIR
2016-05-03Add HasInfo trait to IR, IsDeclaration mixes in HasInfojackkoenig
Change Field from IsDeclaration to HasName Make WDefInstance an IsDeclaration
2016-04-29Change PassUtils to use Utils.time functionjackkoenig
2016-04-29Cleanup Parser comments and imports - No functional changesjackkoenig
2016-04-29Add timing to Parserjackkoenig
2016-04-29Add time function to Utilsjackkoenig
time uses LazyLogging, also delete import PrimOps._ (cyclic reference)
2016-04-26Make sure nested expressions don't make it to the EmitterAndrew Waterman
2016-04-26Split ValidIf from within PrimOpsAndrew Waterman
2016-04-26Fixed the check for bundle equality to allow relative flips to be wrong, but ↵Adam Izraelevitz
the leaf directions are the same
2016-04-26Added flag to parser to turn off using source locators. This allows for ↵Adam Izraelevitz
easier testing, because we don't the source locator information to say a test fails
2016-04-26Fixed bug in recursive check for whether BundleType contains flips.Adam Izraelevitz
2016-04-22Add Uniquify Passjackkoenig
Also add pass to Verilog Compiler list of passes This pass appends '_' to the names of aggregate types that would cause a name collision during LowerTypes.
2016-04-22Refactor LowerTypesjackkoenig
Make loweredName a public utility function of the Pass
2016-04-22Move LowerTypes to its own filejackkoenig
2016-04-22Add utility functions for coverting and computing Gender and Flipjackkoenig
2016-04-22Add isGround and isAggregate functions to Type Utils.jackkoenig
2016-04-22Add optional Info argument to FieldUtils.ToPortjackkoenig
2016-04-22Change FIRRTLException: case class -> class so case classes can extendjackkoenig
2016-04-21Add Expression.tpe accessorAndrew Waterman
Almost all of the code was already there. This is cleaner (and faster) than calling tpe(Expression).
2016-04-21Avoid Lint errors connecting wide signals to narrow onesAndrew Waterman
2016-04-21SplitExpressions should split Mux, not just DoPrimAndrew Waterman
Legalize wasn't always doing its thing because of this.
2016-04-21Emit correct width for ConstProp'd bit extractAndrew Waterman
2016-04-21Strip comments before checking for circuit in Translatorjackkoenig
Fixes #134
2016-04-21Split Expressions on Stop similarly to how they are split on Printjackkoenig
This allows the Print and Stop resulting from Chisel assertions to be guarded by the same expression.
2016-04-21Fix some wonky spacing in Split Expressionsjackkoenig
2016-04-21Run Split Expressions before ConstProp, CSE, and DCEjackkoenig
This gives more expressions to eliminate
2016-04-20Change RemoveCHIRRTL to define port clocks at CHIRRTL port definitionjackkoenig
Invalidate clock at mem definition. Fixes #131
2016-04-20Use a global namespace for VarWidth namesAndrew Waterman
This matches the unstated assumption in InferWidths. Closes #135
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