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getting info for error reporting in new pass/check.
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rocketchip
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for the Parser. Added custom Parser exceptions for better error reporting and checking. Fixed bug in grammar not allowing most keywords as Ids
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accordingly
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structures Compiler and Emitter, deprecate old Passes object, update Driver to use new constructs
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not printing newline before ports
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Scala FIRRTL emission match Stanza FIRRTL for bundles and regs
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preprocessing step. Also added with as scoping keyword
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(notably stop, printf, mux, validif, ubits, sbits, readers, writers, and readwriters are incomplete)
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flying around everywhere
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map.
Also rewrite main so stanza and scala passes can be intermixed.
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ready, has some weird issues when they're not, but also kind of works in that the hardware verifier still reports the right answer, it seems to go to half duty cycle and then do every token twice
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IO between the sim modules.
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need to parse queue module text in midas/Utils.scala, need to create (src, dst) -> Module mapping in midas/Fame.scala
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there yet. Will allow simple bulk connecting at top-level
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