| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2016-09-06 | Added starter code for SMem replacement | Angie | |
| 2016-09-05 | Change null statement to empty begin end (#264) | Colin Schmidt | |
| this eliminates warnings in recent versions of VCS | |||
| 2016-08-25 | emit wires instead of registers for invalid randomization | Howard Mao | |
| Before, the verilog emitter would connect registers to the invalid ports and use random initialization on the generated registers. It is better to generate wires instead and use random assignment on the wires. | |||
| 2016-08-25 | Finer grained control over randomization | Howard Mao | |
| We previously had `ifdef guards on some parts of the emitted verilog to control whether some registers or nets should be given random initial values. These guards were all dependent on the RANDOMIZE macro. However, there were actually three separate cases being controlled 1. Giving random values to disconnected wires 2. Random initialization of registers 3. Random initialization of memories It is possible that the designer would want to switch these three on or off independently in simulation. For instance, the latter two are usually safe because registers and memories will get some definite binary value at power on in the actual circuit, but the first one can be quite dangerous because the undriven wire could be metastable. This change provides separate macros for each of the three sets of guards so that they can be controlled independently. | |||
| 2016-08-18 | emit correct enable signals for memories (#242) | Donggyu | |
| 2016-08-18 | Add MemUtils to aid in interfacing with alternate memory implementations (#244) | Albert Magyar | |
| 2016-08-18 | Remove redundant test and errors.append() in check_types_e(). (#243) | Jim Lawson | |
| 2016-08-17 | Change RW port names (#236) | Angie Wang | |
| * Updated FIRRTL spec + related code for readwrite ports. (write) data -> wdata & mask -> wmask for clarity * Also removed simple.fir that snuck into master branch. | |||
| 2016-08-17 | Fixed cmdline usage string (#235) | Adam Izraelevitz | |
| Now prints usage when given incorrect arguments | |||
| 2016-08-12 | Fix calculation of runtime for ANTLR Parser (#229) | Jack Koenig | |
| 2016-08-12 | Add missing case for connecting ClockType | Megan Wachs | |
| 2016-08-09 | provide parser for naive string (#227) | Donggyu | |
| 2016-08-09 | fix read port enables in RemoveCHIRRTL | Donggyu Kim | |
| read port enables for cmems should always be high | |||
| 2016-08-08 | Don't create output files until the compiler succeeds | Andrew Waterman | |
| Creating the output file preemptively screws up make, as on subsequent executions of make, it thinks the task succeeded. | |||
| 2016-08-05 | Merge pull request #220 from ucb-bar/fix-width-error-msg | Adam Izraelevitz | |
| Bugfix: recursing stmts to remove unknown widths | |||
| 2016-08-04 | Added RemoveEmpty.scala, which removes Empty and nested Blocks (#218) | Adam Izraelevitz | |
| * Added RemoveEmpty.scala, which removes Empty and nested Blocks * Reused squashEmpty from ExpandWhens by moving it to Utils * Squash EmptyStmts in ExpandWhens correctly | |||
| 2016-08-04 | Addd check: bits, tail, head arg width | azidar | |
| 2016-08-04 | Bugfix: recursing stmts to remove unknown widths | azidar | |
| 2016-08-03 | fixes small mistakes in serialize (#216) | Donggyu | |
| 2016-08-02 | Merge pull request #215 from ucb-bar/new-serialize | Adam Izraelevitz | |
| Change serialize to abstract method on FirrtlNode | |||
| 2016-08-02 | Merge pull request #203 from ucb-bar/fix_mem_infer | Adam Izraelevitz | |
| Fix mem infer | |||
| 2016-08-02 | make infer readwrite ports optional | Donggyu Kim | |
| turned on with '--inferRW <circuit name>' | |||
| 2016-08-02 | Change serialize to abstract method on FirrtlNode | Jack Koenig | |
| 2016-08-02 | Merge pull request #214 from ucb-bar/fix-thread-unsafety | Adam Izraelevitz | |
| Fix use of global state in instance loop checking | |||
| 2016-08-02 | Merge pull request #211 from ucb-bar/fix-subaccess | Adam Izraelevitz | |
| Refactor RemoveAccesses and fix bug #210. | |||
| 2016-08-02 | Fix use of global state in instance loop checking | jackkoenig | |
| Also increase sensitivity of thread safety checking Fixes #159 | |||
| 2016-08-01 | Added minor cosmetic changes to RemoveAccesses | azidar | |
| 2016-08-01 | Refactor RemoveAccesses and fix bug #210. | azidar | |
| Added corresponding unit test. | |||
| 2016-07-29 | remove ConstProp in HighFirrtlToMiddleFirrtl | Donggyu Kim | |
| ConstProp before width padding causes errors for SIntLiteral | |||
| 2016-07-28 | InferWidths now only fixes declaration widths | azidar | |
| Then calls InferTypes to propagate inferred widths to expressions. Required upgrading InferTypes to do simple width propagation. Fixes #206 and #200. | |||
| 2016-07-27 | infer readwrite ports for backward compatibility | Donggyu Kim | |
| 2016-07-27 | fix read port enables in RemoveCHIRRTL | Donggyu Kim | |
| read ports are declared outside when clauses and used multiple times, so their enables should be inserted when being replaced | |||
| 2016-07-27 | Forgot to add Annotations.scala | Adam Izraelevitz | |
| 2016-07-27 | Reworked annotation system. Added tenacity and permissibility | Adam Izraelevitz | |
| Conflicts: src/main/scala/firrtl/Compiler.scala src/main/scala/firrtl/LoweringCompilers.scala src/main/scala/firrtl/passes/Inline.scala src/test/scala/firrtlTests/AnnotationTests.scala src/test/scala/firrtlTests/InlineInstancesTests.scala | |||
| 2016-07-27 | Merge pull request #198 from ucb-bar/add-chirrtl-check | Adam Izraelevitz | |
| Added a Chirrtl check for undeclared wires, etc. | |||
| 2016-07-25 | Changed InferTypes to update types if UnknownType or has an UnknownWidth | azidar | |
| Removed InferWidths after ExpandWhens | |||
| 2016-07-25 | Detects and flags cyclic module loops | chick | |
| 2016-07-21 | Added a Chirrtl check for undeclared wires, etc. | azidar | |
| 2016-07-21 | Indentation support for the ANTLR parser (as discussed in #192) (#194) | Kamyar Mohajerani | |
| Indentation support for the ANTLR parser - some clean-up of the parser code (TODO: file input could be improved, more clean-up) - get rid of Translator and specify all syntactic rules in antlr4 grammer - support for else-when shorthand in the grammar - rename Begin to Block which makes more sense | |||
| 2016-07-07 | Guard register randomization with RANDOMIZE, rather than SYNTHESIS | Andrew Waterman | |
| Randomization should be controllable separately. Verilator, for example, already does this if it is passed --x-assign unique; doing it redundantly reduces simulation performance. | |||
| 2016-07-07 | Re-run constant propagation after pad widths | Andrew Waterman | |
| 2016-07-07 | Generalize and clean up constant propagation pass | Andrew Waterman | |
| 2016-07-06 | Emit correct Verilog for SIntLiteral | Andrew Waterman | |
| 2016-07-06 | Only assign garbage to Mem reads for non-power-of-2 depths | Andrew Waterman | |
| 2016-07-06 | Avoid width warnings on Mem garbage assignment | Andrew Waterman | |
| 2016-07-06 | Rely on $fatal vs. $finish, rather than stderr, for stop codes | Andrew Waterman | |
| This approach uses the normal Unix mechanisms, rather than log grepping. | |||
| 2016-07-04 | printf: support '%c' for printing characters | Wesley W. Terpstra | |
| 2016-06-27 | Optionally guard stop with `STOP_COND macro | Andrew Waterman | |
| This allows for testbench handling of pipelined reset, independently of `PRINTF_COND. | |||
| 2016-06-23 | Emit more useful code for stop | Andrew Waterman | |
| - Based upon stop value, use $fatal instead of $finish. This causes the Verilog simulator to signal an error to the OS as appropriate. - Don't guard stop with `PRINTF_COND (only not-`SYNTHESIS). | |||
| 2016-06-10 | Change BoolType from method to val | Jack Koenig | |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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