sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Collapse)	Author
2015-12-08	Refactored MIDAS code into its own repo	jackkoenig

2015-12-07	The transformation works! Kind of, it works fine when everything is alwasy ↵	jackkoenig
	ready, has some weird issues when they're not, but also kind of works in that the hardware verifier still reports the right answer, it seems to go to half duty cycle and then do every token twice
2015-12-06	Working on generating SimTop, need to figure out how to split the top-level ↵	jackkoenig
	IO between the sim modules.
2015-12-04	Everything is broken, need Translator to work on files without a circuit, ↵	jackkoenig
	need to parse queue module text in midas/Utils.scala, need to create (src, dst) -> Module mapping in midas/Fame.scala
2015-12-03	Some stylistic changes and a couple bugfixes to simulation wrapper generation	jackkoenig

2015-12-03	New wrapper generator complete	jackkoenig

2015-12-03	Changing simwrapper to group ports that go to different places, not quite ↵	jackkoenig
	there yet. Will allow simple bulk connecting at top-level