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flying around everywhere
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map.
Also rewrite main so stanza and scala passes can be intermixed.
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ready, has some weird issues when they're not, but also kind of works in that the hardware verifier still reports the right answer, it seems to go to half duty cycle and then do every token twice
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IO between the sim modules.
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need to parse queue module text in midas/Utils.scala, need to create (src, dst) -> Module mapping in midas/Fame.scala
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there yet. Will allow simple bulk connecting at top-level
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updated Makefile to play nicer when firrtl is a submodule, fixed bug in Translator for single line scopes, fixed firrtl-scala script to point to firrtl.Driver instead of old firrtl.Test
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convert object <=> string, added eqv and neqv
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modified Logger slightly, added Primops object for utility functions, minor changes in Utils
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sense for some applications, also fixed up printing to better match stanza implementation
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printing to match stanza implementation
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of printVars still missing. Added Logger class for debug printing
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for unknown width. Also added test to check this
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AST -> String). Uses ANTLRv4 to generate concrete syntax parser
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