| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-01-08 | Avoid enforcing time constrains during coverage tests. (#989) | Jim Lawson |
| 2018-08-29 | Filter resource file names to avoid including the same file multiple times. (... | Jim Lawson |
| 2018-07-20 | Constant prop add (#849) | albertchen-sifive |
| 2018-06-06 | Mechanism to stop verilator from generating VCD file Chisel Issue #808 (#794) | Chick Markley |
| 2018-04-11 | Cleaning up BlackBoxSourceHelper (#786) | Henry Cook |
| 2017-09-21 | Fix problem where wrong verilog file is used. (#661) | Chick Markley |
| 2017-02-01 | Fix anno in backend (#428) | Chick Markley |
| 2017-01-31 | Replace createTempDirectory with createTestDirectory (#427) | Jack Koenig |
| 2017-01-29 | Keep firrtl's simulation environment in sync with chisel's. (#425) | Jim Lawson |
| 2017-01-27 | Move BackendCompilationUtilities into a util package for use by chisel3. (#400) | Jim Lawson |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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