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path: root/src/main/scala/firrtl/transforms
AgeCommit message (Expand)Author
2019-09-16Rename gender to flowSchuyler Eldridge
2019-09-12Add space, s/Github/GitHub/ in DontTouchException (#1177)Schuyler Eldridge
2019-09-05Filter out more filename extensions for blackbox source headers (#1134)Albert Magyar
2019-08-19Refactor exceptions to remove stack trace from user errors (#1157)Jack Koenig
2019-08-13Infer reset (#1068)Jack Koenig
2019-08-07Improve RemoveReset handling of invalid initsSchuyler Eldridge
2019-07-30Fix "since" deprecation, should be "1.2" not "1.3" (#1139)Schuyler Eldridge
2019-07-25Allow name of blackbox resource .f file to change from static value (#1129)Albert Magyar
2019-07-24Add ExpandConnects to TopWiringTransform fixup (#1135)Schuyler Eldridge
2019-07-23more constprop on muxes (#1052)Donggyu Kim
2019-07-19Add SimplifyMems transform to lower memories without splitting (#1111)Albert Magyar
2019-07-08Remove some warnings (#1118)Leway Colin
2019-06-28Remove deprecated ComponentName from CombinationalPath annotation (#1107)Albert Magyar
2019-06-18Use scalafix to remove unused import and deprecated procedure syntax (#1074)Leway Colin
2019-05-09Bugfix: GroupComponents (#1082)Adam Izraelevitz
2019-05-04Add register init to RemoveWires dependencies (#1078)Schuyler Eldridge
2019-04-29Update NoCircuitDedupAnnotation so it's available from firrtl.stage.FirrtlMainJim Lawson
2019-04-25Add ShellOption, DeletedWrapperSchuyler Eldridge
2019-03-29Faster reg constprop (#1067)Albert Magyar
2019-03-26DCE printf and stop statements with constant-0 enablesAndrew Waterman
2019-02-27Add --nodedup option to facilitate FIRRTL to verilog regression testing. (#1035)Jim Lawson
2019-02-25Fix almost all Scaladoc warningsSchuyler Eldridge
2019-02-21Don't let the main module become deduped out of existence. (#1023)Jim Lawson
2019-02-21Prevent Flatten from stripping all annotations (#1024)Schuyler Eldridge
2019-02-14Asynchronous Reset (#1011)Jack Koenig
2019-02-05Do Shr constant propagation in LegalizeSchuyler Eldridge
2019-02-05Missed constprop opportunity (#1009)Andrew Waterman
2019-01-21Merge branch 'master' into top-wiring-aggregatesDavid Biancolin
2019-01-13Suppress unchecked warning in Constant PropagationJack Koenig
2019-01-13Constant Propagate dshl and dshr with constant amountsJack Koenig
2019-01-13Keep constant propagating expressions until done optimizingJack Koenig
2019-01-04Fix GroupComponents to work with unused componentsJack Koenig
2019-01-02Make GroupComponents run ResolveKindsJack Koenig
2018-12-21Enhance CheckCombLoops to support annotated ExtModule paths (#962)Albert Magyar
2018-12-19Add IdentityTransformSchuyler Eldridge
2018-12-13[Top Wiring] Expand top wiring to work on aggregatesDavid Biancolin
2018-12-06Fix bug in dedup where lots of annotations could prevent dedup (#958)Jack Koenig
2018-11-29Replace Mappers with Foreachers in several passes (#954)Albert Magyar
2018-11-16Memoize type of instance refs in RemoveKeywordCollisions (#942)Jack Koenig
2018-11-15Combine cats (#851)Albert Chen
2018-11-07Make CheckCombLoops a RegisteredTransformSchuyler Eldridge
2018-11-07Make DeadCodeElimination a RegisteredTransformSchuyler Eldridge
2018-10-31Use Vector instead of List for bulk renaming in RenameMapJack Koenig
2018-10-31Don't include verilog header files in "FileList" for VCS/Verilator. (#918)Jim Lawson
2018-10-30Instance Annotations (#926)Adam Izraelevitz
2018-10-27Revert "Instance Annotations (#865)" (#925)Adam Izraelevitz
2018-10-24Instance Annotations (#865)Adam Izraelevitz
2018-10-24Better error message on missing BlackBox resourceSchuyler Eldridge
2018-10-12Refactor VerilogRename -> RemoveKeywordCollisionsSchuyler Eldridge
2018-10-01add BlackBoxPathAnno (#903)albertchen-sifive
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