| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-05-19 | Delete black_box_verilog_files.f if we aren't going to create it - fixes #504... | Jim Lawson |
| 2017-05-17 | Make sure not to DCE input-only extmodules unless specified (#590) | Jack Koenig |
| 2017-05-11 | Improved Global Dead Code Elimination (#549) | Jack Koenig |
| 2017-03-06 | Addresses #459. Rewords transform annotations API. | Adam Izraelevitz |
| 2017-02-23 | fix bug in blackboxsourcehelper apply -- pointed to wrong transform | Angie |
| 2017-02-07 | Return a new circuit object after execution (#433) | Colin Schmidt |
| 2017-02-01 | Fix anno in backend (#428) | Chick Markley |
| 2017-01-31 | Blackboxhelper (#418) | Chick Markley |
| 2017-01-20 | Remove merging of source locators during module deduplication | Jack |
| 2016-12-14 | Added NoDedup annotation and test (#397) | Adam Izraelevitz |
| 2016-11-30 | Bugfix: Dedup aggressively (ignore comments) (#375) | Adam Izraelevitz |
| 2016-11-23 | Stringified annotations (#367) | Adam Izraelevitz |
| 2016-11-07 | Fix annotations (#366) | Adam Izraelevitz |
| 2016-11-04 | Add a pass to deduplicate modules | azidar |
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index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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