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path: root/src/main/scala/firrtl/transforms
AgeCommit message (Expand)Author
2018-12-06Fix bug in dedup where lots of annotations could prevent dedup (#958)Jack Koenig
2018-11-29Replace Mappers with Foreachers in several passes (#954)Albert Magyar
2018-11-16Memoize type of instance refs in RemoveKeywordCollisions (#942)Jack Koenig
2018-11-15Combine cats (#851)Albert Chen
2018-11-07Make CheckCombLoops a RegisteredTransformSchuyler Eldridge
2018-11-07Make DeadCodeElimination a RegisteredTransformSchuyler Eldridge
2018-10-31Use Vector instead of List for bulk renaming in RenameMapJack Koenig
2018-10-31Don't include verilog header files in "FileList" for VCS/Verilator. (#918)Jim Lawson
2018-10-30Instance Annotations (#926)Adam Izraelevitz
2018-10-27Revert "Instance Annotations (#865)" (#925)Adam Izraelevitz
2018-10-24Instance Annotations (#865)Adam Izraelevitz
2018-10-24Better error message on missing BlackBox resourceSchuyler Eldridge
2018-10-12Refactor VerilogRename -> RemoveKeywordCollisionsSchuyler Eldridge
2018-10-01add BlackBoxPathAnno (#903)albertchen-sifive
2018-09-26Another TopWiring Bug Fix (Multi-Level Annotations) (#889)alonamid
2018-09-13Do not remove ExtMods with no ports by default (#888)albertchen-sifive
2018-09-07Bug Fixes in TopWiring (#885)alonamid
2018-08-29Filter resource file names to avoid including the same file multiple times. (...Jim Lawson
2018-08-24Update DontTouchAnnotation not found error message (#864)Jack Koenig
2018-08-07Make RemoveWires properly include registers in dependency graphJack Koenig
2018-07-20Constant prop add (#849)albertchen-sifive
2018-07-10Combinational Dependency Annotation (#809)Adam Izraelevitz
2018-06-28Make CheckCombLoops find combinational nodes with self-edges (#837)Albert Magyar
2018-06-13Resolve register clock dependencies in RemoveWires (#823)Schuyler Eldridge
2018-06-11Use attach to connect analogs when grouping (#805)Colin Schmidt
2018-06-06ConstProp attached wires if there is also a port (#818)Jack Koenig
2018-05-29Fix pad (#817)Jack Koenig
2018-05-15Replace truncating add and sub with addw/subw (#800)Jack Koenig
2018-05-11TopWiring Transform (#798)alonamid
2018-05-09Bugfix: ports of a temporary name would break const-prop (#806)Adam Izraelevitz
2018-05-02Deprecate old WiringUtils methods/classes (#801)Schuyler Eldridge
2018-04-16Cleaning up BlackBoxSourceHelper - use absolute file paths. (#789)Jim Lawson
2018-04-11Cleaning up BlackBoxSourceHelper (#786)Henry Cook
2018-04-10Fix bug in Constant Propagation for registers propped to zero (#787)Jack Koenig
2018-04-03Make Dedup properly dedup ExtModules (#781)Jack Koenig
2018-04-02CyclicException identifies a problem node. (#778)Chick Markley
2018-03-28Replace unconnected registers with 0 in Constant Propagation (#776)Jack Koenig
2018-03-27Change throwInternalError to use a String instead of Option[String] (#777)Jack Koenig
2018-03-27Const prop improvement (#772)Jack Koenig
2018-03-23Make Register Update Flattening a Transform and Delete Dangling Nodes (#692)Jack Koenig
2018-03-21GroupModule Transform (#766)Adam Izraelevitz
2018-02-27Refactor Annotations (#721)Jack Koenig
2018-02-27Add log-level debug message for modules that get deduped (#748)Jack Koenig
2018-02-22Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, bu...Adam Izraelevitz
2018-02-16Replacematcherror - catch exceptions and convert to internal error. (#424)Jim Lawson
2018-01-30Make Constant Propagation respect dontTouch on registersJack Koenig
2018-01-30Fix bug incorrectly propagating constants on submodule inputsJack Koenig
2017-12-29Add logger printing for declarations removed by DCEJack Koenig
2017-12-12Add RemoveWires transformJack Koenig
2017-12-12Make object ConstantPropagation utilsJack Koenig
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