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* add FoldADD to const prop, add yosys miter tests
* add option for verilog compiler without optimizations
* rename FoldLogicalOp to FoldCommutativeOp
* add GetNamespace and RenameModules, GetNamespace stores namespace as a ModuleNamespaceAnnotation
* add constant propagation for Tail DoPrims
* add scaladocs for MinimumLowFirrtlOptimization and yosysExpectFalure/Success, add constant propagation for Head DoPrim
* add legalize pass to MinimumLowFirrtlOptimizations, use constPropBitExtract in legalize pass
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Candidate fix for #749
This adds DefRegister netlist ordering to RemoveWires
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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This enables the pattern of attaching "through" a wire to give better
Verilog that also works in Verilator
Use WrappedExpression when combining attaches in ExpandWhens
to ensure no duplication of references in resulting, combined attaches
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* Make VerilogEmitter properly handle pad of width <= width of arg
* Constant prop pads with pad amount <= width of arg
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Replaces old VerilogWrap which didn't work with split expressions and was
actually buggy anyway. This functionality reduces unnecessary intermediates in
emitted Verilog.
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* top wiring transform
* fixup comments
* TopWiring cosmetics
* move prefix into TopWiringAnnotation
* remove test function from transform file
* add ChildrenMap to InstanceGraph API
* use namespaces
* remove wiringUtils from TopWiring pass
* enable multiple output functions
* TopWiring cosmetics, tests and lowform
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The following are deprecated in favor of DiGraph/InstanceGraph:
- firrtl.passes.wiring.Lineage
- firrtl.passes.wiring.WiringUtils.ChildrenMap
- firrtl.passes.wiring.WiringUtils.getChildrenMap
- firrtl.passes.wiring.WiringUtils.getLineage
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
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* Cleaning up BlackBoxSourceHelper - use absolute file paths.
```bash
make[1]: *** No rule to make target `test_run_dir/examples.AccumBlackBox_PeekPokeTest_Verilator345491158/AccumBlackBox.v', needed by `/Users/john/chisel-testers/test_run_dir/examples.AccumBlackBox_PeekPokeTest_Verilator345491158/VAccumBlackBoxWrapper.h'. Stop.
```
since the path `test_run_dir/examples.AccumBlackBox_PeekPokeTest_Verilator345491158/AccumBlackBox.v` does not exist inside `test_run_dir`.
We should either:
- strip the targetDir prefix,
- prepend a `../` to the path,
- use absolute paths
I decided to go with the latter since this makes the least assumptions about the actual downstream processing and we already use absolute paths in other parts of this code.
* Minor cleanup.
- Anonymize make failure comment.
- Use common map syntax.
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Create sources once per module, not once per instance
Clean up writing the file list
Don't prepend file list with '-v's (non-standard and not all verilog)
Change file list file name (not all verilog)
Use ListSets for determinism
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It wasn't properly padding the width of the constant zero.
Also add a test that shows the buggy behavior.
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Needed for special handling in Treadle.
Small refactor that allows users of DiGraph#linearize
to return the first node found in a cycle.
Fixed RemoveWiresTransfrom to handle this.
Added test to show usage of this feature.
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Moved from RemoveValidIf
Also Make RemoveValidIf.getGroundZero public and support Fixed
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Improve constant propagation of connections to references
[skip formal checks]
LEC fails on this PR because this PR actually changes the circuit. The
change is that it constant propagates some additional registers. This is
really just extending #621 to work on more registers that it was
supposed to be propagating anyway.
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* Added grouping pass
* Added InfoMagnet and infomappers
* Changed return type of execute to allow final CircuitState inspection
* Updated dedup. Now is name-agnostic
* Added GroupAndDedup transform
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- Old Annotation renamed to deprecated LegacyAnnotation
- Annotation is now a trait that can be extended
- New JsonProtocol for Annotation [de]serialization
- Replace AnnotationMap with AnnotationSeq
- Deprecate Transform.getMyAnnotations
- Update Transforms
- Turn on deprecation warnings
- Remove deprecated Driver.compile
- Make AnnotationTests abstract with Legacy and Json subclasses
- Add functionality to convert LegacyAnnotations of built-in annos
This will give a noisy warning and is more of a best effort than a
robust solution.
Fixes #475 Closes #609
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but not Emitter. (#717)
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* Catch exceptions and convert to internal error.
We need to update the displayed message to incorporate a line number and text to be used for the issue.
* Cleanup exception handling/throwing.
Re-throw expected (or uncorrectable exceptions).
Provide Utils.getThrowable() to get the first (eldest) or last throwable in the chain.
Update tests to conform to FreeSpec protocol.
* Minor cleanup
Admit we've updated some deprecated ScalaTest methods.
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Two instances of the same module could collide in counting the number of
instances of each Module. This could lead to constants being propagated
on inputs when it is incorrect to do so.
Fixes #734
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This transform replaces all wires with nodes in a legal, flow-forward
order
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Move pad to object ConstantPropagation so other transforms can use it
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instantiated multiple times (#634)
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* initial implementation of InlineDeepTransformation
* rewrote transformation to not have any side effects in terms on inlining that was not annotated to be inlined
* minor rewrites
* renamed transformations to Flatten
* fixes according to review
* added more comments and fixed formating/style
* fixed spacing, minor style fixes
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Fixes issue in https://github.com/freechipsproject/rocket-chip/pull/848
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Names that do not start with '_' are "better" than those that do
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Constant Propagation will not optimize across components marked
dontTouch
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Resolves #600
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We walked the whole set of vertices for every dont touch
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#504 (#551)
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Fixes #589
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