aboutsummaryrefslogtreecommitdiff
path: root/src/main/scala/firrtl/transforms
AgeCommit message (Collapse)Author
2019-09-12Add space, s/Github/GitHub/ in DontTouchException (#1177)Schuyler Eldridge
Adds a space to correct in an exception message. Corrects capitalization in Github to it's official name (GitHub) and adds a link to file an issue. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-05Filter out more filename extensions for blackbox source headers (#1134)Albert Magyar
2019-08-19Refactor exceptions to remove stack trace from user errors (#1157)Jack Koenig
2019-08-13Infer reset (#1068)Jack Koenig
* Add abstract "Reset" which can be inferred to AsyncReset or UInt<1> * Enhance async reset initial value literal check to support aggregates
2019-08-07Improve RemoveReset handling of invalid initsSchuyler Eldridge
This modifies RemoveReset to NOT generate a mux for invalid (IsInvalid) inits. In the case of an invalid init, the reset is converted to a self-connect and no mux is generated. This is implemented as a new, initial pass over the module to populate a set of all invalid signals. During the subsequent, circuit-modifying pass, this invalid set is queried to special case the handling of invalid inits. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-30Fix "since" deprecation, should be "1.2" not "1.3" (#1139)Schuyler Eldridge
- Fixes BlackBoxSourceHelper deprecation "since"
2019-07-25Allow name of blackbox resource .f file to change from static value (#1129)Albert Magyar
* Allow name of blackbox resource .f file to change from static value * Restore fileListName as a deprecated def per Jack's feedback * Support both local and absolute paths for .f resource files
2019-07-24Add ExpandConnects to TopWiringTransform fixup (#1135)Schuyler Eldridge
This fixes a bug in the TopWiringTransform when wiring aggregates by adding ExpandConnects to its list of fixup passes. TopWiringTransform is MidForm => MidForm, but when wiring aggregates, it will output bulk connects. This violates the MidForm prerequisite that ExpandConnects has run. Symptomatically, this will manifest as match errors in LowerTypes if a user tries to use the TopWiringTransform on aggregates. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-07-23more constprop on muxes (#1052)Donggyu Kim
2019-07-19Add SimplifyMems transform to lower memories without splitting (#1111)Albert Magyar
* Add SimplifyMems transform to lower memories without splitting * Remove spurious anonymous function
2019-07-08Remove some warnings (#1118)Leway Colin
2019-06-28Remove deprecated ComponentName from CombinationalPath annotation (#1107)Albert Magyar
2019-06-18Use scalafix to remove unused import and deprecated procedure syntax (#1074)Leway Colin
* Add sbt-scalafix * Add scalafix guide to README * Remove Unused Import * Remove deprecated procedure syntax
2019-05-09Bugfix: GroupComponents (#1082)Adam Izraelevitz
* Added test to GroupComponentsSpec demonstrating bug * Added bugfix to GroupComponents for invalid ports of grouped instances
2019-05-04Add register init to RemoveWires dependencies (#1078)Schuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-04-29Update NoCircuitDedupAnnotation so it's available from firrtl.stage.FirrtlMainJim Lawson
2019-04-25Add ShellOption, DeletedWrapperSchuyler Eldridge
Abstracts away option writing such that users no longer have to understand scopt semantics. This adds a ShellOption class and a HasShellOptions trait for something which provides one or more ShellOptions. This refactors the FIRRTL codebase to use this style of option specification. Adds and uses DeletedWrapper to automatically generate DeletedAnnotations. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-03-29Faster reg constprop (#1067)Albert Magyar
* Improve memoization for register const prop
2019-03-26DCE printf and stop statements with constant-0 enablesAndrew Waterman
This gets rid of about 10% of the generated Verilog in the rocket-chip default config.
2019-02-27Add --nodedup option to facilitate FIRRTL to verilog regression testing. (#1035)Jim Lawson
* Add --nodedup option to facilitate FIRRTL to verilog regression testing. * Short-circuit the DedupModules transform if NoCircuitDedupAnnotation exists.
2019-02-25Fix almost all Scaladoc warningsSchuyler Eldridge
This fixes all Scaladoc warnings except for those trying to link to Java. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-21Don't let the main module become deduped out of existence. (#1023)Jim Lawson
2019-02-21Prevent Flatten from stripping all annotations (#1024)Schuyler Eldridge
2019-02-14Asynchronous Reset (#1011)Jack Koenig
Fixes #219 * Adds AsyncResetType (similar to ClockType) * Registers with reset signal of type AsyncResetType are async reset registers * Registers with async reset can only be reset to literal values * Add initialization logic for async reset registers
2019-02-05Do Shr constant propagation in LegalizeSchuyler Eldridge
This uses the foldShiftRight method of the ConstantPropagation Transform when legalizing Shr PrimOps. This has the effect of removing literals with bit extracts from the MinimumVerilogCompiler. This makes the formerly private foldShiftRight method of a public method of the ConstantPropagation companion object. Tests in the MimimumVerilogCompilerSpec are updated to check that Shr is handled as intended. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-02-05Missed constprop opportunity (#1009)Andrew Waterman
* Enhance constant propagation across registers * Add more elaborate test case for register const prop
2019-01-21Merge branch 'master' into top-wiring-aggregatesDavid Biancolin
2019-01-13Suppress unchecked warning in Constant PropagationJack Koenig
2019-01-13Constant Propagate dshl and dshr with constant amountsJack Koenig
Fixes #990 h/t @pentin-as and @abejgonzalez
2019-01-13Keep constant propagating expressions until done optimizingJack Koenig
2019-01-04Fix GroupComponents to work with unused componentsJack Koenig
Previously, components that did not affect the output would cause exceptions because they were missing from the label2group Map. This commit treats them as "reachable" by the ports so they are included in the default "ungrouped" group.
2019-01-02Make GroupComponents run ResolveKindsJack Koenig
This fixes an issue where expressions created by GroupComponents would be improperly lowered because they were not marked as references to instance ports.
2018-12-21Enhance CheckCombLoops to support annotated ExtModule paths (#962)Albert Magyar
2018-12-19Add IdentityTransformSchuyler Eldridge
This adds an identity transform that applies an identity function to some CircuitState, i.e., it just returns the original CircuitState. This is useful for transform generators that may, for edge cases, generate an empty transform sequence. Other classes (e.g., Compiler) have explicit or implicit requirements that a transform sequence is non-empty. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-12-13[Top Wiring] Expand top wiring to work on aggregatesDavid Biancolin
2018-12-06Fix bug in dedup where lots of annotations could prevent dedup (#958)Jack Koenig
Iterating on a HashSet could cause identical modules (including annotations) to not dedup
2018-11-29Replace Mappers with Foreachers in several passes (#954)Albert Magyar
2018-11-16Memoize type of instance refs in RemoveKeywordCollisions (#942)Jack Koenig
Huge performance improvement when you have lots of ports for a given module. Also split up some long implicit argument lines.
2018-11-15Combine cats (#851)Albert Chen
- Add firrtl.transforms.CombineCats - Use CombineCats in LowFirrtlOptimization - Modify Verilog emitter to allow for nested Cat DoPrims - Modify firrtlEquivalenceTest to write input FIRRTL string to test directory
2018-11-07Make CheckCombLoops a RegisteredTransformSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-11-07Make DeadCodeElimination a RegisteredTransformSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-10-31Use Vector instead of List for bulk renaming in RenameMapJack Koenig
2018-10-31Don't include verilog header files in "FileList" for VCS/Verilator. (#918)Jim Lawson
When constructing the black box helper file list (firrtl_black_box_resource_files.f), filter out Verilog header files (*.vh) - Fixes #917
2018-10-30Instance Annotations (#926)Adam Izraelevitz
Formerly #865 Major Code Changes/Features Added: Added Target trait as replacement for Named Added TargetToken as token in building Target Added GenericTarget as a catch-all Target Added CircuitTarget, ModuleTarget, ReferenceTarget, and InstanceTarget Added ResolvePaths annotation Added EliminateTargetPaths (and helper class DuplicationHelper) Updated Dedup to work with instance annotations Updated RenameMap to work with instance annotations DCE & ConstantProp extend ResolveAnnotationPaths
2018-10-27Revert "Instance Annotations (#865)" (#925)Adam Izraelevitz
This reverts commit 7e2f787e125227dc389d5cf1d09717748ecfed2e.
2018-10-24Instance Annotations (#865)Adam Izraelevitz
Added Target, which now supports Instance Annotations. See #865 for details.
2018-10-24Better error message on missing BlackBox resourceSchuyler Eldridge
This wraps interactions with a BlackBox resource file such that a FileNotFoundException are wrapped in a BlackBoxNotFoundException and rethrown. This provides a better, verbose error message to the user and avoids a FileNotFoundException showing up as an internal FIRRTL error. This adds tests that the expected exception is thrown for both BlackBoxResourceAnno and BlackBoxResourceAnno. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-10-12Refactor VerilogRename -> RemoveKeywordCollisionsSchuyler Eldridge
This moves VerilogRename out of Passes.scala and genericizes it as the new Transform KemoveKeywordCollisions. This new Transform will remove keywords for arbitrary sets of reserved keyword. This adds VerilogRename back as a class instead of an object. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-10-01add BlackBoxPathAnno (#903)albertchen-sifive
2018-09-26Another TopWiring Bug Fix (Multi-Level Annotations) (#889)alonamid
When different levels of the circuit were annotated, the TopWiring signals of the lower levels would "run-over" the TopWiring signals of the higher levels
generated by cgit v1.2.3 (git 2.25.1) at 2026-04-29 06:25:49 +0000