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path: root/src/main/scala/firrtl/transforms
AgeCommit message (Expand)Author
2020-07-17Propagate source locators to register update always blocks (#1743)Jack Koenig
2020-07-14Make TopWiringTransform run before LowerTypes (#1750)Schuyler Eldridge
2020-07-08dedup: use structural sha256 hash instead of agnostify and serialize (#1731)Kevin Laeufer
2020-07-01Fix unchecked type in ManipulateNames (#1726)Schuyler Eldridge
2020-06-26Add ConvertAsserts transform to map asserts to Verilog-friendly nodesAlbert Magyar
2020-06-25Add ManipulateNamesAllowlistResultAnnotationSchuyler Eldridge
2020-06-25Refactor RemoveKeywordCollisions->ManipulateNamesSchuyler Eldridge
2020-06-24verification: clarify the meaning of verification statement in warning messag...Kevin Laeufer
2020-06-23Don't Dedup modules if it would change semantics (#1713)Jack Koenig
2020-06-23Basic model checking API (#1653)Tom Alcorn
2020-06-22Convert PreservesAll to explicit invalidates=falseSchuyler Eldridge
2020-06-03Revert: Generalize keyword collision to name manipulation, Add {Lower,Upper}C...Schuyler Eldridge
2020-06-02Fix performance pathology in DedupModules (#1654)Jack Koenig
2020-05-28Implement InstanceTarget Behavior for Dedup + EliminateTargetPaths (#1539)Albert Chen
2020-05-26[API change] Absorb repetitive WIR nodes into IRAlbert Magyar
2020-05-21RenameMap: remove implicit rename chaining (#1591)Albert Chen
2020-05-20Add scaladoc for LogicNode and tighten LowForm-only constraint (#1635)Albert Magyar
2020-05-18Don't try deduping the main module of a circuit (#1594)Albert Magyar
2020-05-18Canonicalize init of regs with zero as reset in RemoveReset (#1627)Albert Magyar
2020-05-13Remove accidental hashing of all Modules in DedupJack Koenig
2020-05-13Remove expensive .distinct in DedupJack Koenig
2020-05-13Add features.{LowerCaseNames, UpperCaseNames} transformsSchuyler Eldridge
2020-05-13Refactor RemoveKeywordCollisions->ManipulateNamesSchuyler Eldridge
2020-05-11Add andr, orr, xorr literal constant propagationSchuyler Eldridge
2020-05-04Add LegalizeAndReductionsTransformJack Koenig
2020-04-22s/dependents/optionalPrerequisiteOf/Schuyler Eldridge
2020-04-22Mixin DependencyAPIMigration to all TransformsSchuyler Eldridge
2020-04-06Avoid using deprecated 'Gender' objectsAlbert Magyar
2020-03-30Make InlineCasts invalidate LegalizeClocksAlbert Magyar
2020-03-30Avoid generating illegal part-selects in InlineCastsAlbert Magyar
2020-03-30Don't use postfix operator in transforms.FlattenSchuyler Eldridge
2020-03-26Eliminate warnings on `sbt doc` and `sbt unidoc` (#1470)Chick Markley
2020-03-17Add method to CheckCompLoops which returns its full netlist (#1458)David Biancolin
2020-03-12Add Support for FPGA Bitstream Preset-registers (#1050)John's Brew
2020-03-11Don't const-prop a register's self-init (#1441)Albert Magyar
2020-03-11Migrate to DependencyAPISchuyler Eldridge
2020-03-09Provide an annotation mix-in that marks RTs as dontTouch (#1433)David Biancolin
2020-03-04Incorporate new AddNot formal regression testAlbert Magyar
2020-03-04Revert "Verilog emitter transform InlineNots (#1270)"Albert Magyar
2020-02-18Remove last connect semantics from reset inference (#1396)Jack Koenig
2020-02-13Constant prop binary PrimOps with matching argumentsAlbert Magyar
2020-02-12Fixing lint error: x + -1 (#1374)Adam Izraelevitz
2020-02-07Refactor handling of reg const prop entries to cover more casesAlbert Magyar
2020-02-06Better register const prop through speculative de-optimizationAlbert Magyar
2020-02-06Add constant prop to async regs (#1355)Adam Izraelevitz
2020-02-03Dedup: check if moduleOpt exists before getting (#1323)Albert Chen
2020-01-20clean up warnings: trim unused imports (#1315)John Ingalls
2020-01-15Verilog emitter transform InlineBitExtractions (#1296)John Ingalls
2020-01-07Fix literals cast to Clocks in Print and StopJack Koenig
2020-01-07Remove unnecessary $signed casts for PrimOps in Verilog EmitterJack Koenig
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