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2018-12-25Performance fix of Uniquify for deep bundles (#980)Adam Izraelevitz
2018-12-18Give better error when mport references non-existant memory. (#975)Paul Rigge
* Give better error when mport references non-existent memory * Closes #796
2018-11-29Replace Mappers with Foreachers in several passes (#954)Albert Magyar
2018-11-27Add foreach as alternative to map (#952)Adam Izraelevitz
* Added Foreachers * Changed CheckTypes to use foreach * Check widths now uses foreach * Finished merge, added foreachers to added stmts * Address reviewer feedback
2018-11-26Make return types of util functions more specific (#949)Albert Magyar
2018-11-07Make ClockListAnnotation a RegisteredTransformSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-11-07Make InlineInstances a RegisteredTransformSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-11-07Add MemLibOptions RegisteredLibrarySchuyler Eldridge
This shows an example of using a RegisteredLibrary, with the appropriate META-INF ServiceLoader entry, that adds options from the InferReadWrite and ReplSeqMem transforms. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-11-07Make ReplSeqMem mixin HasScoptOptionsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-11-07Make InferReadWrite mixin HasScoptOptionsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-11-07Add FirrtlOptionsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-11-05Better error message for UninferredWidth exceptionSchuyler Eldridge
This changes the CheckTypes.UniferredWidth exception to include the pretty printed Target that was uninferred and suggests to the user that they may have forgotten to assign to it. This changes the CheckTypes pass to communicate the necessary Target information during AST traversal such that when an uninferred width is found, the Target is known and available. This also adds one test checking the message of the UniferredWidth exception. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-11-02Fix renaming in UniquifyPorts (#930)Albert Chen
2018-10-31Remove all uses of get_flip and deprecateJack Koenig
It is O(n) and every use is in an O(n) iteration resulting in O(n^2). Same information can be extracted from create_exps which happens to also be called at every use of get_flip.
2018-10-31Use Vector instead of List for bulk renaming in RenameMapJack Koenig
2018-10-31Speed up LowerTypes by replacing foldLeft + List appends with flatMapJack Koenig
2018-10-31Speed up ExpandWhens by replacing foldLeft + List appends with flatMapJack Koenig
2018-10-31Speed up ExpandConnects by replacing foldLeft + List appends with flatMapJack Koenig
2018-10-30Instance Annotations (#926)Adam Izraelevitz
Formerly #865 Major Code Changes/Features Added: Added Target trait as replacement for Named Added TargetToken as token in building Target Added GenericTarget as a catch-all Target Added CircuitTarget, ModuleTarget, ReferenceTarget, and InstanceTarget Added ResolvePaths annotation Added EliminateTargetPaths (and helper class DuplicationHelper) Updated Dedup to work with instance annotations Updated RenameMap to work with instance annotations DCE & ConstantProp extend ResolveAnnotationPaths
2018-10-27Revert "Instance Annotations (#865)" (#925)Adam Izraelevitz
This reverts commit 7e2f787e125227dc389d5cf1d09717748ecfed2e.
2018-10-24Instance Annotations (#865)Adam Izraelevitz
Added Target, which now supports Instance Annotations. See #865 for details.
2018-10-12Refactor VerilogRename -> RemoveKeywordCollisionsSchuyler Eldridge
This moves VerilogRename out of Passes.scala and genericizes it as the new Transform KemoveKeywordCollisions. This new Transform will remove keywords for arbitrary sets of reserved keyword. This adds VerilogRename back as a class instead of an object. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-10-12Verilog renaming uses "_", works on whole ASTSchuyler Eldridge
Summary of changes to firrtl.passes.VerilogRename: - Use "_" to mangle names that conflict with Verilog keywords (previously "$") - Rewrite to operate on the whole AST to propogate mangled ports and module names - Make VerilogRename a Transform (was previously a Pass) - Renames are now propagated - Adds documentation for new VerilogRename This makes the VerilogRename Transform (previously a Pass) use an underscore ('_') instead of a dollar sign ('$') to mangle names that conflict with Verilog keywords. This prevents problems with potentially buggy tools that are not expecting '$' in Verilog names. This reimplements VerilogRename to be safe for name collisions that may occur anywhere in the AST, e.g., in ports, module names, circuit names, or in any statements/expressions. Previously, names were only mangled in statements and in place. This resulted in problems where renames of ports in a child's namespace would not be guaranteed to be mangled the same way in a parent's namespace. The algorithm is reimplemented to walk all modules in reverse topological order (from leafs to main) and relying on a RenameMap to track name changes. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-10-03Inlining uses "_", respects namespacesSchuyler Eldridge
Summary of changes: - Use "_" as an inlining delimiter instead of "$" - Makes inlining avoid namespace conflicts This changes the delimiter used for inlining to "_" instead of "$". This avoids problems with buggy parsers that may not handle "$" correctly. As ClockListTransform relies on the explicit use of "$", the delimiter is a FIRRTL-private val that the ClockListTransform overrides (to the original "$"). Namespace conflicts could occur previously, but are very rare as users will almost never use "$" in a name (even though it's allowed by both the FIRRTL and Verilog specifications). Moving to "_" increases the probability of namespace conflicts occurring. This adds explicit checking that inlined names will not introduce namespace conflicts and that generated names are prefix unique (as defined in the spec). Note: inlined modules may not have unique prefixes. A test is included that this is the case and an ignored test shows what prefix uniqueness would look like. MISC: - [skip chisel tests]: Changing the delimiter causes the Chisel InlineSpec to fail as this explicitly checks for "$". Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-10-03Make some Uniquify methods private [firrtl]Schuyler Eldridge
This makes findValidPrefix and enumerateNames both private to FIRRTL (previously, these were private). This enables their use for name generation by other FIRRTL passes/transforms. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-09-26Enforce port uniqueness in Chirrtl/High ChecksSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-08-23Fix NoDedupMem to be cognizant of Module scope (#876)Jack Koenig
Previously, mems marked no dedup would prevent mems with the same instance name in other modules from deduping
2018-07-20Constant prop add (#849)albertchen-sifive
* add FoldADD to const prop, add yosys miter tests * add option for verilog compiler without optimizations * rename FoldLogicalOp to FoldCommutativeOp * add GetNamespace and RenameModules, GetNamespace stores namespace as a ModuleNamespaceAnnotation * add constant propagation for Tail DoPrims * add scaladocs for MinimumLowFirrtlOptimization and yosysExpectFalure/Success, add constant propagation for Head DoPrim * add legalize pass to MinimumLowFirrtlOptimizations, use constPropBitExtract in legalize pass
2018-07-10Fix bug in zero-width renaming (#845)Jack Koenig
Previously, Vecs of Bundles that contained a zero-width element would result in a ClassCastException
2018-07-10InferWidths: improve performance (#846)edwardcwang
On circuits with large numbers of width inferences, prepend to a linked list instead of appending and having to make a copy. Fixes #842
2018-07-03Improve code generation for smem wmode and [w]mask ports (#834)Andrew Waterman
[skip formal checks] LEC passes with Formality * Improve code generation for smem RW-port wmode port A common case for these port-enables is wen = valid & write ren = valid & !write which the RW-port transform currently turns into en = (valid & write) | (valid & !write) wmode = valid & write because it proved `wen` and `ren` are mutually exclusive via `write`. Synthesis tools can trivially optimize `en` to `valid`, so that's not a problem, but the wmode field can't be optimized if going into a black box. This PR instead sets `wmode` to whatever node was used to prove mutual exclusion, which is always a simpler expression. In this case: en = (valid & write) | (valid & !write) wmode = write * In RemoveCHIRRTL, infer mask relative to port definition Previously, it was inferred relative to the memory definition causing the mask condition to be redundantly conjoined with the enable signal. Also enable ReplSeqMems to ignore all ValidIfs (not just on Clocks) to improve QoR.
2018-07-02Make ZeroWidth properly rename removed empty aggregates (#839)Jack Koenig
Fixes #756
2018-06-11Add utilities for UInt and SInt literals (#815)Jack Koenig
Also minor cleanup to literal construction in Visitor
2018-06-06ConstProp attached wires if there is also a port (#818)Jack Koenig
This enables the pattern of attaching "through" a wire to give better Verilog that also works in Verilator Use WrappedExpression when combining attaches in ExpandWhens to ensure no duplication of references in resulting, combined attaches
2018-05-30Makes ExpandWhens preserve connect Infoschick
* Collects Infos found for symbols * Merges multiple sources for symbol into MultiInfo * Restores these Infos on connect statements. * Add test showing preserved Infos * Changed ++ methods on the Info sub-classes * Ignore NoInfo being added * Fixed way adding was implemented in MultiInfo * Made InfoMap a class which defines the default value function
2018-05-21Fix more problems with zero width things. (#779)grebe
This should close #757. It should also allow for stop() and printf() to be used with zero-width fields.
2018-05-15Replace truncating add and sub with addw/subw (#800)Jack Koenig
Replaces old VerilogWrap which didn't work with split expressions and was actually buggy anyway. This functionality reduces unnecessary intermediates in emitted Verilog.
2018-05-02Deprecate old WiringUtils methods/classes (#801)Schuyler Eldridge
The following are deprecated in favor of DiGraph/InstanceGraph: - firrtl.passes.wiring.Lineage - firrtl.passes.wiring.WiringUtils.ChildrenMap - firrtl.passes.wiring.WiringUtils.getChildrenMap - firrtl.passes.wiring.WiringUtils.getLineage Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-04-26Fix bug in VerilogMemDelays (#795)Jack Koenig
* Change VerilogMemDelays to put new Statements at end of Module Fixes #547 This is instead of putting them right after the modified DefMemory which could result in use before declaration errors for things that feed into the new logic. * Adds tests that show VerilogMemDelays crashing. (#792)
2018-03-28Replace unconnected registers with 0 in Constant Propagation (#776)Jack Koenig
Moved from RemoveValidIf Also Make RemoveValidIf.getGroundZero public and support Fixed
2018-03-27Change throwInternalError to use a String instead of Option[String] (#777)Jack Koenig
2018-03-26Make WiringTransform remove its used annotations (#774)Schuyler Eldridge
* Make WiringTransform remove its used annotations Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-03-21GroupModule Transform (#766)Adam Izraelevitz
* Added grouping pass * Added InfoMagnet and infomappers * Changed return type of execute to allow final CircuitState inspection * Updated dedup. Now is name-agnostic * Added GroupAndDedup transform
2018-03-19Masks for zero-width fields of mems should be width zero. (#763)grebe
Closes #666.
2018-03-02Reduce Statement nesting in Wiring Pass (#751)Jack Koenig
Large amounts of Wiring could result in huge nesting of Statements. This could cause stack overflows using the Mappers. Fixed by no longer nesting Statements in Wiring Pass.
2018-03-01[name change] Use LsbLargerThanMsbException (#740)Schuyler Eldridge
Use the standard convention of 'XxYyException' for the previously named LsbLargerThanMsb Exception. h/t @kevintownsend Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-02-27Refactor Annotations (#721)Jack Koenig
- Old Annotation renamed to deprecated LegacyAnnotation - Annotation is now a trait that can be extended - New JsonProtocol for Annotation [de]serialization - Replace AnnotationMap with AnnotationSeq - Deprecate Transform.getMyAnnotations - Update Transforms - Turn on deprecation warnings - Remove deprecated Driver.compile - Make AnnotationTests abstract with Legacy and Json subclasses - Add functionality to convert LegacyAnnotations of built-in annos This will give a noisy warning and is more of a best effort than a robust solution. Fixes #475 Closes #609
2018-02-22Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, ↵Adam Izraelevitz
but not Emitter. (#717)
2018-02-21Change primop arg type (#587)Adam Izraelevitz
* Changed primops to not accept mixed-type args * Changed return type of sub of two uints to uint * Added negative tests * Removed rocket.fir. Manually changed RocketCore to not mix mul arg types. Added integration tests * Clarified test description and remove println * Fixed use of throwInternalError
2018-02-16Replacematcherror - catch exceptions and convert to internal error. (#424)Jim Lawson
* Catch exceptions and convert to internal error. We need to update the displayed message to incorporate a line number and text to be used for the issue. * Cleanup exception handling/throwing. Re-throw expected (or uncorrectable exceptions). Provide Utils.getThrowable() to get the first (eldest) or last throwable in the chain. Update tests to conform to FreeSpec protocol. * Minor cleanup Admit we've updated some deprecated ScalaTest methods.
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