aboutsummaryrefslogtreecommitdiff
path: root/src/main/scala/firrtl/passes
AgeCommit message (Expand)Author
2018-12-25Performance fix of Uniquify for deep bundles (#980)Adam Izraelevitz
2018-12-18Give better error when mport references non-existant memory. (#975)Paul Rigge
2018-11-29Replace Mappers with Foreachers in several passes (#954)Albert Magyar
2018-11-27Add foreach as alternative to map (#952)Adam Izraelevitz
2018-11-26Make return types of util functions more specific (#949)Albert Magyar
2018-11-07Make ClockListAnnotation a RegisteredTransformSchuyler Eldridge
2018-11-07Make InlineInstances a RegisteredTransformSchuyler Eldridge
2018-11-07Add MemLibOptions RegisteredLibrarySchuyler Eldridge
2018-11-07Make ReplSeqMem mixin HasScoptOptionsSchuyler Eldridge
2018-11-07Make InferReadWrite mixin HasScoptOptionsSchuyler Eldridge
2018-11-07Add FirrtlOptionsSchuyler Eldridge
2018-11-05Better error message for UninferredWidth exceptionSchuyler Eldridge
2018-11-02Fix renaming in UniquifyPorts (#930)Albert Chen
2018-10-31Remove all uses of get_flip and deprecateJack Koenig
2018-10-31Use Vector instead of List for bulk renaming in RenameMapJack Koenig
2018-10-31Speed up LowerTypes by replacing foldLeft + List appends with flatMapJack Koenig
2018-10-31Speed up ExpandWhens by replacing foldLeft + List appends with flatMapJack Koenig
2018-10-31Speed up ExpandConnects by replacing foldLeft + List appends with flatMapJack Koenig
2018-10-30Instance Annotations (#926)Adam Izraelevitz
2018-10-27Revert "Instance Annotations (#865)" (#925)Adam Izraelevitz
2018-10-24Instance Annotations (#865)Adam Izraelevitz
2018-10-12Refactor VerilogRename -> RemoveKeywordCollisionsSchuyler Eldridge
2018-10-12Verilog renaming uses "_", works on whole ASTSchuyler Eldridge
2018-10-03Inlining uses "_", respects namespacesSchuyler Eldridge
2018-10-03Make some Uniquify methods private [firrtl]Schuyler Eldridge
2018-09-26Enforce port uniqueness in Chirrtl/High ChecksSchuyler Eldridge
2018-08-23Fix NoDedupMem to be cognizant of Module scope (#876)Jack Koenig
2018-07-20Constant prop add (#849)albertchen-sifive
2018-07-10Fix bug in zero-width renaming (#845)Jack Koenig
2018-07-10InferWidths: improve performance (#846)edwardcwang
2018-07-03Improve code generation for smem wmode and [w]mask ports (#834)Andrew Waterman
2018-07-02Make ZeroWidth properly rename removed empty aggregates (#839)Jack Koenig
2018-06-11Add utilities for UInt and SInt literals (#815)Jack Koenig
2018-06-06ConstProp attached wires if there is also a port (#818)Jack Koenig
2018-05-30Makes ExpandWhens preserve connect Infoschick
2018-05-21Fix more problems with zero width things. (#779)grebe
2018-05-15Replace truncating add and sub with addw/subw (#800)Jack Koenig
2018-05-02Deprecate old WiringUtils methods/classes (#801)Schuyler Eldridge
2018-04-26Fix bug in VerilogMemDelays (#795)Jack Koenig
2018-03-28Replace unconnected registers with 0 in Constant Propagation (#776)Jack Koenig
2018-03-27Change throwInternalError to use a String instead of Option[String] (#777)Jack Koenig
2018-03-26Make WiringTransform remove its used annotations (#774)Schuyler Eldridge
2018-03-21GroupModule Transform (#766)Adam Izraelevitz
2018-03-19Masks for zero-width fields of mems should be width zero. (#763)grebe
2018-03-02Reduce Statement nesting in Wiring Pass (#751)Jack Koenig
2018-03-01[name change] Use LsbLargerThanMsbException (#740)Schuyler Eldridge
2018-02-27Refactor Annotations (#721)Jack Koenig
2018-02-22Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, bu...Adam Izraelevitz
2018-02-21Change primop arg type (#587)Adam Izraelevitz
2018-02-16Replacematcherror - catch exceptions and convert to internal error. (#424)Jim Lawson
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-09 13:05:09 +0000