aboutsummaryrefslogtreecommitdiff
path: root/src/main/scala/firrtl/passes
AgeCommit message (Expand)Author
2017-05-25Fix performance bug in ZeroWidth (#594)Jack Koenig
2017-05-12Bugfix: renaming instance ports was broken. (#588)Adam Izraelevitz
2017-05-12Fix pad, second try (#465)Adam Izraelevitz
2017-05-11Refactor WIR WSub{Field,Index,Access} - rename exp -> expr #521 (#586)Jim Lawson
2017-05-10Update rename2 (#478)Adam Izraelevitz
2017-05-03Add checks on register clock and reset types (#33) (#553)Albert Magyar
2017-04-13Speed up CSE by doing CSE on node expression before recording the node (#543)Jack Koenig
2017-04-04DecorateMems should not delete annoations (#523)Colin Schmidt
2017-04-03Find a single cycle from potentially many in a combinational SCCAlbert Magyar
2017-03-29Fix bug where zero width expressions in nodes wouldn't get zeroed (#514)Jack Koenig
2017-03-23Add pass to detect combinational loopsAlbert Magyar
2017-03-23Pass now subclasses Transform (#477)Adam Izraelevitz
2017-03-22Fixed zero width perf bug #502Adam Izraelevitz
2017-03-22Fix unapply of pinAdam Izraelevitz
2017-03-22Bugfix: apply/unapply of PinAnnotation brokenazidar
2017-03-09make sure infer-rw works for exclusive when statements (#481)Donggyu
2017-03-09Sint tests and change in serialization (#456)Adam Izraelevitz
2017-03-06Zero width (#402)Adam Izraelevitz
2017-03-06Addresses #459. Rewords transform annotations API.Adam Izraelevitz
2017-03-03Bugfix: InlineInstances must prefix instancesAdam Izraelevitz
2017-02-23move more general utils out of memutils, mov WIR helpers to WIR.scala and upd...Angie
2017-02-23messed up clocktype matchAngie
2017-02-23added more helpersAngie
2017-02-22[stevo]: Adams fixStevo Bailey
2017-02-21Implementation of nodedupe mem (#447)Colin Schmidt
2017-02-14Add support for Analog types in partial connect (#435)Jack Koenig
2017-02-14Fixes #441, ConvertFixedToSInt not recursing expsAdam Izraelevitz
2017-02-07Rework Attach to work on arbitrary Analog hierarchies (#415)Jack Koenig
2017-02-06Fix stack overflow from massive MaxWidth chains during width inference (#407)Jack Koenig
2017-01-27Fix signed types (#422)Angie Wang
2017-01-23Add FixedType to uniqueify match statement.Paul Rigge
2017-01-22use new annotations correctly for wiring (#416)Colin Schmidt
2017-01-19Verilog rem fix (#404)grebe
2016-12-13Add MaxWidth of 1,000,000 bitsjackkoenig
2016-12-13Move CheckWidths to its own filejackkoenig
2016-12-07Bugfix: add Neg to high form check (#384)Adam Izraelevitz
2016-12-05Add check for muxing between clocks (#360)Jack Koenig
2016-12-05Bugfix: expand whens not voiding memories (#380)Adam Izraelevitz
2016-11-23Stringified annotations (#367)Adam Izraelevitz
2016-11-21Bugfix: exponential runtime of pull muxes (#379)Adam Izraelevitz
2016-11-21Rewrote inline xform to fix quadratic perf. bug (#377)Adam Izraelevitz
2016-11-15Fixed multi wiring (#368)Adam Izraelevitz
2016-11-14Fix wrong omitting same clocked nondirect children (#374)Adam Izraelevitz
2016-11-10Added additional optimizationsazidar
2016-11-09Added optimizations to for better width inferenceazidar
2016-11-09Bugfix: removed recursive removal in infer widthsazidar
2016-11-07Clock List Transform (#365)Adam Izraelevitz
2016-11-07Fix annotations (#366)Adam Izraelevitz
2016-11-05Fix CHIRRTL bugs (#355)Donggyu
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-09 12:28:51 +0000