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* Updated FIRRTL spec + related code for readwrite ports.
(write) data -> wdata & mask -> wmask for clarity
* Also removed simple.fir that snuck into master branch.
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read port enables for cmems should always be high
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Bugfix: recursing stmts to remove unknown widths
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* Added RemoveEmpty.scala, which removes Empty and nested Blocks
* Reused squashEmpty from ExpandWhens by moving it to Utils
* Squash EmptyStmts in ExpandWhens correctly
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Change serialize to abstract method on FirrtlNode
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Fix mem infer
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turned on with '--inferRW <circuit name>'
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Fix use of global state in instance loop checking
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Also increase sensitivity of thread safety checking
Fixes #159
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Added corresponding unit test.
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Then calls InferTypes to propagate inferred widths to expressions.
Required upgrading InferTypes to do simple width propagation.
Fixes #206 and #200.
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read ports are declared outside when clauses and used multiple times, so their enables should be inserted when being replaced
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Conflicts:
src/main/scala/firrtl/Compiler.scala
src/main/scala/firrtl/LoweringCompilers.scala
src/main/scala/firrtl/passes/Inline.scala
src/test/scala/firrtlTests/AnnotationTests.scala
src/test/scala/firrtlTests/InlineInstancesTests.scala
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Added a Chirrtl check for undeclared wires, etc.
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Indentation support for the ANTLR parser
- some clean-up of the parser code (TODO: file input could be improved, more clean-up)
- get rid of Translator and specify all syntactic rules in antlr4 grammer
- support for else-when shorthand in the grammar
- rename Begin to Block which makes more sense
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trait AST -> abstract class FirrtlNode
Move all IR to new package ir
Add import of firrtl.ir._
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Add simple documentation
trait PrimOp -> abstract class PrimOp
Move PrimOp case objects to object PrimOps
Rename PrimOp case objects to match concrete syntax
Overrwrite toString for more canonical serialization
Update some PrimOps utility functions
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trait Expression -> abstract class Expression
Ref -> Reference
abbrev. exp -> expr
Add abstract class Literal
UIntValue -> UIntLiteral extends Literal
SIntValue -> SIntLiteral extends Literal
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trait Stmt -> abstract class Statement (to match Expression)
abbrev. exp -> expr
BulkConnect -> PartialConnect
camelCase things that were snake_case
case class Empty() -> case object EmptyStmt
Change >120 character Statements to multiline
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Add simple documentation
trait Width -> abstract class Width
case class UnknownWidth -> case object UnknownWidth
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Add simple documentation
Flip -> Orientation
trait Orientation -> abstract class Orientation
Orientation case objects to upper camel case
REVERSE -> Flip
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trait Type -> abstract class Type
case class ClockType() -> case object ClockType
case class UnknownType() -> case object UnknownType
Add GroundType and AggregateType
ClockType has width of IntWidth(1)
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Add simple documentation
Change Direction case objects to upper camel case
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trait Module -> abstract class DefModule
InModule -> Module (match concrete syntax)
ExModule -> ExtModule (match concrete syntax)
Add simple scaladoc for each one
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Addresses #184
Problem was that the width inferencer must assume a minimal width
for self-referencing widths contained in a MaxWidth. Otherwise, it
cannot solve the constraint.
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Fix bug in FIRRTL width inference, refactor associated functions
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Update check high form
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When folding over lists for MinWidth and MaxWidth, would assume 0 as a start
value. 0 persists through MinWidth resulting in under-constraining
The functions were also refactored to be more readable and aligned with scala
style/best practices.
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Made obsolete by #120
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Canonicalizes catching/throwing PassExceptions.
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also check for it int unittest
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Transforms are new unit of modularity within the compiler.
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This is to start moving stuff out of Emitter and into separate passes
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