| Age | Commit message (Collapse) | Author |
|---|
|
* Added pass name to debug logger
* Addresses #459. Rewords transform annotations API.
Now, any annotation not propagated by a transform is considered deleted.
A new DeletedAnnotation is added in place of it.
* Added more stylized debugging style
* WIP: make pass transform
* WIP: All tests pass, need to pull master
* Cleaned up PR
* Added rename updates to all core transforms
* Added more rename tests, and bugfixes
* Renaming tracks non-leaf subfields
E.g. given:
wire x: {a: UInt<1>, b: UInt<1>[2]}
Annotating x.b will eventually annotate x_b_0 and x_b_1
* Bugfix instance rename lowering broken
* Address review comments
* Remove check for seqTransform, UnknownForm too restrictive check
|
|
|
|
|
|
|
|
|
|
Now, any annotation not propagated by a transform is considered deleted.
A new DeletedAnnotation is added in place of it.
|
|
update uses
|
|
|
|
|
|
This allows the replseqmem transform to not deduplicate
some memories, based on their name.
|
|
* type conversions between sint/fixed and uint added at memory interfaces for replseqmem
* turns out asFixed requires bp as constant in PrimOps (really should be documented)
* fixed legalizeconnects to handle FixedPt
* added tests for replseqmem failure with signed types
|
|
Restricts annotations to be string-based (and thus less typesafe)
Makes annotations more easily serializable and interact with Chisel
|
|
* Fixed multi wiring
* Minor style changes
|
|
Added clocklist transform
|
|
getMyAnnotations now returns Seq[Annotation]
Changed test to check number of annotations is the same
|
|
Replace with more sensible comment to see LICENSE rather than including the
whole license in every file
|
|
* Transform Ids now handled by Class[_ <: Transform] instead of magic numbers
* Transforms define inputForm and outputForm
* Custom transforms can be inserted at runtime into compiler or the Driver
* Current "built-in" custom transforms handled via above mechanism
* Verilog-specific passes moved to the Verilog emitter
|
|
|
|
* Keep package name + directory structure consistent
This annoyed me so heres a PR
* fix InferReadWrite references
* delete .ConvertFixedToSInt.scala.swo
|
|
Added wiring pass and simple test
|
|
* fix imports in InferReadWrite
* improve reference & name resolution in ReplSeqMem
* add comments
|
|
Adds support for Integer, Double/Real, and String parameters in external
modules. Also add name field to extmodules so that emitted name can be
different from Firrtl name. This is important because parameterized extmodules
will frequently have differing IO even though they need to be emitted as
instantiating the same Verilog module.
|
|
|
|
* toBitMask cat direction should be consistent with data
* minor comment updates
* moved remaining mem passes/utils to memlib
* changed again so that data, mask are consistent. data element 0, bit 0 = LSB (on RHS) when concatenated
|
|
duplcate memory detection should be in circuit-level, not in module-level
|
|
* Reorganized memory blackboxing
Moved to new package memlib
Added comments
Moved utility functions around
Removed unused AnnotateValidMemConfigs.scala
* Fixed tests to pass
* Use DefAnnotatedMemory instead of AppendableInfo
* Broke passes up into simpler passes
AnnotateMemMacros ->
(ToMemIR, ResolveMaskGranularity)
UpdateDuplicateMemMacros ->
(RenameAnnotatedMemoryPorts, ResolveMemoryReference)
* Fixed to make tests run
* Minor changes from code review
* Removed vim comments and renamed ReplSeqMem
|
