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path: root/src/main/scala/firrtl/passes/memlib
AgeCommit message (Expand)Author
2020-08-14All of src/ formatted with scalafmtchick
2020-08-13Remove LegacyAnnotation and [most] MoultingYaml (#1833)Jack Koenig
2020-07-30ir: use Serializer.serialize where possible (#1809)Kevin Laeufer
2020-07-29[2.13] replace `= Unit` with `= ()`Kevin Laeufer
2020-07-29MemConf: build list of tuples and turn it into a map at the endKevin Laeufer
2020-07-29[2.13] convert toSeq and toMap where necessary to compileKevin Laeufer
2020-06-22Convert PreservesAll to explicit invalidates=falseSchuyler Eldridge
2020-05-01Add missing invalidations to some transforms (#1541)Schuyler Eldridge
2020-04-22s/dependents/optionalPrerequisiteOf/Schuyler Eldridge
2020-04-22Mixin DependencyAPIMigration to all TransformsSchuyler Eldridge
2020-03-11Migrate to DependencyAPISchuyler Eldridge
2020-02-18Revert "Repl seq mem renaming (#1286)" (#1399)Jack Koenig
2020-02-12Repl seq mem renaming (#1286)Jack Koenig
2020-02-12Support MemConfs with very deep memories (#1367)Jerry Zhao
2019-11-19Error when blackboxing memories with unsupported masking (#1238)Abraham Gonzalez
2019-11-18Make updated type info available in VerilogMemDelays (#1243)Albert Magyar
2019-10-21Fix write-first mem enable handling in VerilogMemDelaysAlbert Magyar
2019-10-18Upstream intervals (#870)Adam Izraelevitz
2019-09-30Implement read-first memories in VerilogMemDelaysAlbert Magyar
2019-09-30Add read-under-write checks for memory emissionAlbert Magyar
2019-09-30Improve read-under-write parameter supportAlbert Magyar
2019-09-16Rename gender to flowSchuyler Eldridge
2019-08-01Followup to PR #1142chick
2019-07-08Remove some warnings (#1118)Leway Colin
2019-06-18Use scalafix to remove unused import and deprecated procedure syntax (#1074)Leway Colin
2019-04-25Add ShellOption, DeletedWrapperSchuyler Eldridge
2019-04-25Add FirrtlStage, make Driver compatibility layerSchuyler Eldridge
2019-04-22Change Memory Depth to a BigInt (#1075)Jack Koenig
2019-03-19Designs with no SeqMems should produce empty MemConf strings, and this should...John Wright
2019-03-07Add a data structure for memory conf reading and writing (#1041)John Wright
2019-02-11Fix typo for -c: compiler -> circuit (#1014)John Wright
2019-02-01Mem helpers (#1010)Albert Magyar
2018-11-29Replace Mappers with Foreachers in several passes (#954)Albert Magyar
2018-11-27Add foreach as alternative to map (#952)Adam Izraelevitz
2018-11-26Make return types of util functions more specific (#949)Albert Magyar
2018-11-07Add MemLibOptions RegisteredLibrarySchuyler Eldridge
2018-11-07Make ReplSeqMem mixin HasScoptOptionsSchuyler Eldridge
2018-11-07Make InferReadWrite mixin HasScoptOptionsSchuyler Eldridge
2018-11-07Add FirrtlOptionsSchuyler Eldridge
2018-08-23Fix NoDedupMem to be cognizant of Module scope (#876)Jack Koenig
2018-07-03Improve code generation for smem wmode and [w]mask ports (#834)Andrew Waterman
2018-04-26Fix bug in VerilogMemDelays (#795)Jack Koenig
2018-03-27Change throwInternalError to use a String instead of Option[String] (#777)Jack Koenig
2018-03-21GroupModule Transform (#766)Adam Izraelevitz
2018-03-19Masks for zero-width fields of mems should be width zero. (#763)grebe
2018-02-27Refactor Annotations (#721)Jack Koenig
2018-02-22Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, bu...Adam Izraelevitz
2018-02-16Replacematcherror - catch exceptions and convert to internal error. (#424)Jim Lawson
2018-01-15WiringTransform Refactor (#648)Schuyler Eldridge
2017-05-27Prep for Scala 2.12 (#557)Jim Lawson
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