| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-11-29 | Replace Mappers with Foreachers in several passes (#954) | Albert Magyar |
| 2018-04-26 | Fix bug in VerilogMemDelays (#795) | Jack Koenig |
| 2017-03-23 | Pass now subclasses Transform (#477) | Adam Izraelevitz |
| 2016-11-04 | Cleanup license at top of every file (#364) | Jack Koenig |
| 2016-11-01 | fix bug. remove spurious connect that reassigns node (#358) | Scott Beamer |
| 2016-10-30 | Keep package name + directory structure consistent (#354) | Colin Schmidt |
| 2016-10-23 | Fix bitmask (#346) | Angie Wang |
 |
index : sfcX | |
| Scala FIRRTL Compiler for chiselX |
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