aboutsummaryrefslogtreecommitdiff
path: root/src/main/scala/firrtl/passes/VerilogModulusCleanup.scala
AgeCommit message (Collapse)Author
2020-03-11Migrate to DependencyAPISchuyler Eldridge
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-16Rename gender to flowSchuyler Eldridge
The following names are changed: - gender -> flow - Gender -> Flow - MALE -> SourceFlow - FEMALE -> SinkFlow - BIGENDER -> DuplexFlow - UNKNOWNGENDER -> UnknownFlow Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2017-03-23Pass now subclasses Transform (#477)Adam Izraelevitz
2017-01-19Verilog rem fix (#404)grebe
* Add pass that fixes up widths with modulus operator for verilog * Add basic test for Verilog emission of Rem * Oops, left in some printlns.
generated by cgit v1.2.3 (git 2.25.1) at 2026-05-02 08:03:02 +0000