sfcX - Scala FIRRTL Compiler for chiselX

Age	Commit message (Expand)	Author
2018-12-18	Give better error when mport references non-existant memory. (#975)	Paul Rigge
2018-07-03	Improve code generation for smem wmode and [w]mask ports (#834)	Andrew Waterman
2018-02-22	Add tests for #702. Adds Utility functions. Allows clock muxing in FIRRTL, bu...	Adam Izraelevitz
2017-05-10	Update rename2 (#478)	Adam Izraelevitz
2017-03-23	Pass now subclasses Transform (#477)	Adam Izraelevitz
2016-11-05	Fix CHIRRTL bugs (#355)	Donggyu
2016-11-04	Cleanup license at top of every file (#364)	Jack Koenig
2016-10-11	Scala style cleanup take 5 (#324)	Chick Markley
2016-09-27	remove unnecessary parentheses	chick
2016-09-25	remove unnecessary blocks	chick
2016-09-25	use name parameter when calling a function with boolean constant	chick
2016-09-23	use .head instead of (0)	chick
2016-09-21	Fix clock connections in InferReadWrite (#310)	Donggyu
2016-09-14	fix enable signal inferecne for smems' read ports (#289)	Donggyu
2016-09-13	Fix a lurking width-inference bug; improve adjacent style (#298)	Andrew Waterman
2016-09-13	use BoolType for UIntType(IntWidth(1))	Donggyu Kim
2016-09-13	clean up MemUtils	Donggyu Kim
2016-09-08	refactor RemoveCHIRRTL	Donggyu Kim
2016-09-08	split Passes.scala into multiple files(InferTypes.scala, Resolves.scala, Remo...	Donggyu Kim