aboutsummaryrefslogtreecommitdiff
path: root/src/main/scala/firrtl/passes/Passes.scala
AgeCommit message (Collapse)Author
2020-04-10Split Passes.scala into separate files (#1496)Adam Izraelevitz
* Split Passes.scala into separate files * Add imports of implicit things Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-03-11Migrate to DependencyAPISchuyler Eldridge
Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-16Rename gender to flowSchuyler Eldridge
The following names are changed: - gender -> flow - Gender -> Flow - MALE -> SourceFlow - FEMALE -> SinkFlow - BIGENDER -> DuplexFlow - UNKNOWNGENDER -> UnknownFlow Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-08-19Refactor exceptions to remove stack trace from user errors (#1157)Jack Koenig
2019-06-18Use scalafix to remove unused import and deprecated procedure syntax (#1074)Leway Colin
* Add sbt-scalafix * Add scalafix guide to README * Remove Unused Import * Remove deprecated procedure syntax
2019-05-04Use UnknownKind instead misrepresented NodeKind (#1076)Leway Colin
2019-02-22Add Width Constraints with Annotations (#956)Albert Chen
* refactor InferWidths to allow for extra contraints, add InferWidthsWithAnnos * add test cases * add ResolvedAnnotationPaths trait to InferWidthsWithAnnos * remove println * cleanup tests * remove extraneous constraints * use foreachStmt instead of mapStmt * remove support for aggregates * fold InferWidthsWithAnnos into InferWidths * throw exception if ref not found, check for annos before AST walk
2019-02-05Do Shr constant propagation in LegalizeSchuyler Eldridge
This uses the foldShiftRight method of the ConstantPropagation Transform when legalizing Shr PrimOps. This has the effect of removing literals with bit extracts from the MinimumVerilogCompiler. This makes the formerly private foldShiftRight method of a public method of the ConstantPropagation companion object. Tests in the MimimumVerilogCompilerSpec are updated to check that Shr is handled as intended. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-10-31Remove all uses of get_flip and deprecateJack Koenig
It is O(n) and every use is in an O(n) iteration resulting in O(n^2). Same information can be extracted from create_exps which happens to also be called at every use of get_flip.
2018-10-31Speed up ExpandConnects by replacing foldLeft + List appends with flatMapJack Koenig
2018-10-12Refactor VerilogRename -> RemoveKeywordCollisionsSchuyler Eldridge
This moves VerilogRename out of Passes.scala and genericizes it as the new Transform KemoveKeywordCollisions. This new Transform will remove keywords for arbitrary sets of reserved keyword. This adds VerilogRename back as a class instead of an object. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-10-12Verilog renaming uses "_", works on whole ASTSchuyler Eldridge
Summary of changes to firrtl.passes.VerilogRename: - Use "_" to mangle names that conflict with Verilog keywords (previously "$") - Rewrite to operate on the whole AST to propogate mangled ports and module names - Make VerilogRename a Transform (was previously a Pass) - Renames are now propagated - Adds documentation for new VerilogRename This makes the VerilogRename Transform (previously a Pass) use an underscore ('_') instead of a dollar sign ('$') to mangle names that conflict with Verilog keywords. This prevents problems with potentially buggy tools that are not expecting '$' in Verilog names. This reimplements VerilogRename to be safe for name collisions that may occur anywhere in the AST, e.g., in ports, module names, circuit names, or in any statements/expressions. Previously, names were only mangled in statements and in place. This resulted in problems where renames of ports in a child's namespace would not be guaranteed to be mangled the same way in a parent's namespace. The algorithm is reimplemented to walk all modules in reverse topological order (from leafs to main) and relying on a RenameMap to track name changes. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2018-07-20Constant prop add (#849)albertchen-sifive
* add FoldADD to const prop, add yosys miter tests * add option for verilog compiler without optimizations * rename FoldLogicalOp to FoldCommutativeOp * add GetNamespace and RenameModules, GetNamespace stores namespace as a ModuleNamespaceAnnotation * add constant propagation for Tail DoPrims * add scaladocs for MinimumLowFirrtlOptimization and yosysExpectFalure/Success, add constant propagation for Head DoPrim * add legalize pass to MinimumLowFirrtlOptimizations, use constPropBitExtract in legalize pass
2018-05-15Replace truncating add and sub with addw/subw (#800)Jack Koenig
Replaces old VerilogWrap which didn't work with split expressions and was actually buggy anyway. This functionality reduces unnecessary intermediates in emitted Verilog.
2017-09-22Fix string lit (#663)Jack Koenig
Refactor StringLit to use String instead of Array[Byte]
2017-05-11Refactor WIR WSub{Field,Index,Access} - rename exp -> expr #521 (#586)Jim Lawson
2017-03-23Pass now subclasses Transform (#477)Adam Izraelevitz
2017-02-14Add support for Analog types in partial connect (#435)Jack Koenig
Also add support for width inference
2017-02-07Rework Attach to work on arbitrary Analog hierarchies (#415)Jack Koenig
* Rework Attach to work on arbitrary Analog hierarchies If there are zero or one Analog sources in an Attach (source meaning wire or parent module port), then the Attach will be emitted as a simple point to point connection. In the general case, alias is used for simulation while forwards and backwards assigns for synthesis. Verilator does not currently support the general case so an `ifdef Verilator `error is emitted. * Add helper functions for creating WRef from Reg and Wire
2017-01-27Fix signed types (#422)Angie Wang
* type conversions between sint/fixed and uint added at memory interfaces for replseqmem * turns out asFixed requires bp as constant in PrimOps (really should be documented) * fixed legalizeconnects to handle FixedPt * added tests for replseqmem failure with signed types
2016-11-21Bugfix: exponential runtime of pull muxes (#379)Adam Izraelevitz
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
Replace with more sensible comment to see LICENSE rather than including the whole license in every file
2016-10-17Add fixed point type (#322)Adam Izraelevitz
* WIP: Adding FixedType to Firrtl proper Got simple example running through width inference Checks should be ok Need to look into FixedLiteral more * Added simple test for fixed types * Added asFixedPoint to primops * Added tail case for FixedType * Added ConvertFixedToSInt.scala Added pass to MiddleToLowerFirrtl transform * Replace AsFixedType with AsSInt in fixed removal * Bugfix: constant from asFixed not deleted * Added unit test for bulk connect * Fixed partial connect bug #241 * Fixed missing case for FixedPoint in legalizeConnect * Add FixedMathSpec that demonstrates some problems with FixedPointMath * Fixed test and ConvertToSInt to pass. Negative binary points not easily supported, needs much more time to implement. * Refactored checking neg widths Make checking for negative binary points easier * Added tests for inferring many FixedType ops shl, shr, cat, bits, head, tail, setbp, shiftbp * Handle bpshl, bpshr, bpset in ConvertFixedToSInt Changed name from shiftbp -> bpshl, bpshr Change name from setbp -> bpset Added more tests * Added set binary point test that fails * Added simple test for zero binary point * gitignore fixes for antlr intermediate dir and intellij dir * removed unused imports retool the fixed point with zero binary point test * simplified example of inability to set binary point to zero * Temporary fix for zero-width binary point This fix allows for all widths to be zero, but since this is a feature I am working on next, I'm not going to bother with a more stringent check. * change version for dsp tools * Removed extra temporary file * Fixed merge bug * Fixed another merge bug * Removed commented out/unrelated files * Removed snake case
2016-10-11Scala style cleanup take 5 (#324)Chick Markley
* working through variable shrouding * working through variable shrouding * working through variable shadowing * working through variable shadowing hmm there are some very fragile match {} in Passes * working through variable shadowing hmm there are some very fragile match {} in Passes * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * working through variable shadowing * Fixes suggested by Adam
2016-09-27remove unnecessary parentheseschick
2016-09-25Spec features added: AnalogType and Attach (#295)Adam Izraelevitz
* Spec features added: AnalogType and Attach AnalogType(width: Width): - Concrete syntax: wire x: AnalogType<10> - New groundtype, very restricted in use cases. - Can only declare ports and wires with Analog type - Analog types are never equivalent, thus if x and y have Analog types: x <= y is never legal. Attach(info: Info, source: Expression, exprs: Seq[Expression]): - Concrete syntax: attach x to (y, z) - New statement - Source can be any groundtyped expression (UInt, SInt, Analog, Clock) - Exprs must have an Analog type reference an instance port - Source and exprs must have identical widths Included WDefInstanceConnector to enable emission of Verilog inout Should be mostly feature complete. Need to update spec if PR gets accepted. * Fixed bug where invalidated ports aren't handled * Bugfix for VerilogPrep Intermediate wires for invalidated instance ports were not invalidated * Bugfix: calling create_exp with name/tpe Returns unknown gender, which was passing through Caused temporary wire to not be declared Because Verilog is dumb, undeclared wires are assumed to be 1bit signals * Addressed donggyukim's style comments * Reworked pass to only allow analog types in attach Restrict source to be only wire or port kind Much simpler implementation, almost identical functionality Clearer semantics (i think?) * Fixup bugs from pulling in new changes from master * comments for type eqs and small style fixes
2016-09-25remove unnecessary blockschick
example 1 s"${x}" example 2 case blah => { ??? }
2016-09-23Use parens on Unit methodschick
2016-09-23use .head instead of (0)chick
2016-09-13use BoolType for UIntType(IntWidth(1))Donggyu Kim
2016-09-13use case object for KindDonggyu Kim
2016-09-13clean up Passes.scalaDonggyu Kim
2016-09-12Add legalization of pad operation on literals.Jack
Performing a pad on SInt literals results in linting warnings in Verilator. This commit replaces pad operations on literal values with a literal of the correct width.
2016-09-12Legalize bit select. Run Legalize after PadWidths.Jack
Bit selecting a literal resulted in invalid Verilog. Legalize now deals with this by replacing any bits select of UInt or SInt literals with a new literal composed of the selected bits. Legalize also is now run after PadWidths because that pass introduces this issue. Fixes #170
2016-09-12Change Legalize Connect to respect SIntJack
Legalize will wrap the rhs of a connect statement with a bit select primop if the lhs is of smaller width than the rhs. This bit select is now wrapped in a asSInt cast if the original rhs was an SInt so that is has the correct type. Fixes #173
2016-09-12Change Legalize Shift Right to respect SIntjackkoenig
Fix bug where Legalize was generating a bit select for SInts without then casting to SInt Fixes #169
2016-09-08split Passes.scala into multiple files(InferTypes.scala, Resolves.scala, ↵Donggyu Kim
RemoveCHIRRTL.scala)
2016-09-07put InferWidths in a seperate file and fix spacesDonggyu Kim
2016-09-07clean up PullMuxes & ExpandConnectsDonggyu Kim
2016-09-07remove Utils.ONEDonggyu Kim
2016-09-07remove Utils.tpeDonggyu Kim
2016-09-06replace flatMap with foldLeft in create_expsDonggyu Kim
internal implementation for flatMap seems to be inefficient
2016-08-17Change RW port names (#236)Angie Wang
* Updated FIRRTL spec + related code for readwrite ports. (write) data -> wdata & mask -> wmask for clarity * Also removed simple.fir that snuck into master branch.
2016-08-09fix read port enables in RemoveCHIRRTLDonggyu Kim
read port enables for cmems should always be high
2016-08-04Bugfix: recursing stmts to remove unknown widthsazidar
2016-08-02Merge pull request #215 from ucb-bar/new-serializeAdam Izraelevitz
Change serialize to abstract method on FirrtlNode
2016-08-02Merge pull request #203 from ucb-bar/fix_mem_inferAdam Izraelevitz
Fix mem infer
2016-08-02Change serialize to abstract method on FirrtlNodeJack Koenig
2016-08-01Refactor RemoveAccesses and fix bug #210.azidar
Added corresponding unit test.
2016-07-28InferWidths now only fixes declaration widthsazidar
Then calls InferTypes to propagate inferred widths to expressions. Required upgrading InferTypes to do simple width propagation. Fixes #206 and #200.
generated by cgit v1.2.3 (git 2.25.1) at 2026-03-09 10:55:28 +0000